Xenomai API  2.6.5
ni_tio.h
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1 
21 #ifndef __ANALOGY_NI_TIO_H__
22 #define __ANALOGY_NI_TIO_H__
23 
24 #include <analogy/analogy_driver.h>
25 
26 #ifdef CONFIG_PCI
27 #include "mite.h"
28 #endif
29 
30 enum ni_gpct_register {
31  NITIO_G0_Autoincrement_Reg,
32  NITIO_G1_Autoincrement_Reg,
33  NITIO_G2_Autoincrement_Reg,
34  NITIO_G3_Autoincrement_Reg,
35  NITIO_G0_Command_Reg,
36  NITIO_G1_Command_Reg,
37  NITIO_G2_Command_Reg,
38  NITIO_G3_Command_Reg,
39  NITIO_G0_HW_Save_Reg,
40  NITIO_G1_HW_Save_Reg,
41  NITIO_G2_HW_Save_Reg,
42  NITIO_G3_HW_Save_Reg,
43  NITIO_G0_SW_Save_Reg,
44  NITIO_G1_SW_Save_Reg,
45  NITIO_G2_SW_Save_Reg,
46  NITIO_G3_SW_Save_Reg,
47  NITIO_G0_Mode_Reg,
48  NITIO_G1_Mode_Reg,
49  NITIO_G2_Mode_Reg,
50  NITIO_G3_Mode_Reg,
51  NITIO_G0_LoadA_Reg,
52  NITIO_G1_LoadA_Reg,
53  NITIO_G2_LoadA_Reg,
54  NITIO_G3_LoadA_Reg,
55  NITIO_G0_LoadB_Reg,
56  NITIO_G1_LoadB_Reg,
57  NITIO_G2_LoadB_Reg,
58  NITIO_G3_LoadB_Reg,
59  NITIO_G0_Input_Select_Reg,
60  NITIO_G1_Input_Select_Reg,
61  NITIO_G2_Input_Select_Reg,
62  NITIO_G3_Input_Select_Reg,
63  NITIO_G0_Counting_Mode_Reg,
64  NITIO_G1_Counting_Mode_Reg,
65  NITIO_G2_Counting_Mode_Reg,
66  NITIO_G3_Counting_Mode_Reg,
67  NITIO_G0_Second_Gate_Reg,
68  NITIO_G1_Second_Gate_Reg,
69  NITIO_G2_Second_Gate_Reg,
70  NITIO_G3_Second_Gate_Reg,
71  NITIO_G01_Status_Reg,
72  NITIO_G23_Status_Reg,
73  NITIO_G01_Joint_Reset_Reg,
74  NITIO_G23_Joint_Reset_Reg,
75  NITIO_G01_Joint_Status1_Reg,
76  NITIO_G23_Joint_Status1_Reg,
77  NITIO_G01_Joint_Status2_Reg,
78  NITIO_G23_Joint_Status2_Reg,
79  NITIO_G0_DMA_Config_Reg,
80  NITIO_G1_DMA_Config_Reg,
81  NITIO_G2_DMA_Config_Reg,
82  NITIO_G3_DMA_Config_Reg,
83  NITIO_G0_DMA_Status_Reg,
84  NITIO_G1_DMA_Status_Reg,
85  NITIO_G2_DMA_Status_Reg,
86  NITIO_G3_DMA_Status_Reg,
87  NITIO_G0_ABZ_Reg,
88  NITIO_G1_ABZ_Reg,
89  NITIO_G0_Interrupt_Acknowledge_Reg,
90  NITIO_G1_Interrupt_Acknowledge_Reg,
91  NITIO_G2_Interrupt_Acknowledge_Reg,
92  NITIO_G3_Interrupt_Acknowledge_Reg,
93  NITIO_G0_Status_Reg,
94  NITIO_G1_Status_Reg,
95  NITIO_G2_Status_Reg,
96  NITIO_G3_Status_Reg,
97  NITIO_G0_Interrupt_Enable_Reg,
98  NITIO_G1_Interrupt_Enable_Reg,
99  NITIO_G2_Interrupt_Enable_Reg,
100  NITIO_G3_Interrupt_Enable_Reg,
101  NITIO_Num_Registers,
102 };
103 
104 static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
105  counter_index)
106 {
107  switch (counter_index) {
108  case 0:
109  return NITIO_G0_Autoincrement_Reg;
110  break;
111  case 1:
112  return NITIO_G1_Autoincrement_Reg;
113  break;
114  case 2:
115  return NITIO_G2_Autoincrement_Reg;
116  break;
117  case 3:
118  return NITIO_G3_Autoincrement_Reg;
119  break;
120  default:
121  BUG();
122  break;
123  }
124  return 0;
125 }
126 
127 static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
128 {
129  switch (counter_index) {
130  case 0:
131  return NITIO_G0_Command_Reg;
132  break;
133  case 1:
134  return NITIO_G1_Command_Reg;
135  break;
136  case 2:
137  return NITIO_G2_Command_Reg;
138  break;
139  case 3:
140  return NITIO_G3_Command_Reg;
141  break;
142  default:
143  BUG();
144  break;
145  }
146  return 0;
147 }
148 
149 static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
150  counter_index)
151 {
152  switch (counter_index) {
153  case 0:
154  return NITIO_G0_Counting_Mode_Reg;
155  break;
156  case 1:
157  return NITIO_G1_Counting_Mode_Reg;
158  break;
159  case 2:
160  return NITIO_G2_Counting_Mode_Reg;
161  break;
162  case 3:
163  return NITIO_G3_Counting_Mode_Reg;
164  break;
165  default:
166  BUG();
167  break;
168  }
169  return 0;
170 }
171 
172 static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
173  counter_index)
174 {
175  switch (counter_index) {
176  case 0:
177  return NITIO_G0_Input_Select_Reg;
178  break;
179  case 1:
180  return NITIO_G1_Input_Select_Reg;
181  break;
182  case 2:
183  return NITIO_G2_Input_Select_Reg;
184  break;
185  case 3:
186  return NITIO_G3_Input_Select_Reg;
187  break;
188  default:
189  BUG();
190  break;
191  }
192  return 0;
193 }
194 
195 static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
196  counter_index)
197 {
198  switch (counter_index) {
199  case 0:
200  case 1:
201  return NITIO_G01_Joint_Reset_Reg;
202  break;
203  case 2:
204  case 3:
205  return NITIO_G23_Joint_Reset_Reg;
206  break;
207  default:
208  BUG();
209  break;
210  }
211  return 0;
212 }
213 
214 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
215  counter_index)
216 {
217  switch (counter_index) {
218  case 0:
219  case 1:
220  return NITIO_G01_Joint_Status1_Reg;
221  break;
222  case 2:
223  case 3:
224  return NITIO_G23_Joint_Status1_Reg;
225  break;
226  default:
227  BUG();
228  break;
229  }
230  return 0;
231 }
232 
233 static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
234  counter_index)
235 {
236  switch (counter_index) {
237  case 0:
238  case 1:
239  return NITIO_G01_Joint_Status2_Reg;
240  break;
241  case 2:
242  case 3:
243  return NITIO_G23_Joint_Status2_Reg;
244  break;
245  default:
246  BUG();
247  break;
248  }
249  return 0;
250 }
251 
252 static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
253 {
254  switch (counter_index) {
255  case 0:
256  case 1:
257  return NITIO_G01_Status_Reg;
258  break;
259  case 2:
260  case 3:
261  return NITIO_G23_Status_Reg;
262  break;
263  default:
264  BUG();
265  break;
266  }
267  return 0;
268 }
269 
270 static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
271 {
272  switch (counter_index) {
273  case 0:
274  return NITIO_G0_LoadA_Reg;
275  break;
276  case 1:
277  return NITIO_G1_LoadA_Reg;
278  break;
279  case 2:
280  return NITIO_G2_LoadA_Reg;
281  break;
282  case 3:
283  return NITIO_G3_LoadA_Reg;
284  break;
285  default:
286  BUG();
287  break;
288  }
289  return 0;
290 }
291 
292 static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
293 {
294  switch (counter_index) {
295  case 0:
296  return NITIO_G0_LoadB_Reg;
297  break;
298  case 1:
299  return NITIO_G1_LoadB_Reg;
300  break;
301  case 2:
302  return NITIO_G2_LoadB_Reg;
303  break;
304  case 3:
305  return NITIO_G3_LoadB_Reg;
306  break;
307  default:
308  BUG();
309  break;
310  }
311  return 0;
312 }
313 
314 static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
315 {
316  switch (counter_index) {
317  case 0:
318  return NITIO_G0_Mode_Reg;
319  break;
320  case 1:
321  return NITIO_G1_Mode_Reg;
322  break;
323  case 2:
324  return NITIO_G2_Mode_Reg;
325  break;
326  case 3:
327  return NITIO_G3_Mode_Reg;
328  break;
329  default:
330  BUG();
331  break;
332  }
333  return 0;
334 }
335 
336 static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
337 {
338  switch (counter_index) {
339  case 0:
340  return NITIO_G0_SW_Save_Reg;
341  break;
342  case 1:
343  return NITIO_G1_SW_Save_Reg;
344  break;
345  case 2:
346  return NITIO_G2_SW_Save_Reg;
347  break;
348  case 3:
349  return NITIO_G3_SW_Save_Reg;
350  break;
351  default:
352  BUG();
353  break;
354  }
355  return 0;
356 }
357 
358 static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
359 {
360  switch (counter_index) {
361  case 0:
362  return NITIO_G0_Second_Gate_Reg;
363  break;
364  case 1:
365  return NITIO_G1_Second_Gate_Reg;
366  break;
367  case 2:
368  return NITIO_G2_Second_Gate_Reg;
369  break;
370  case 3:
371  return NITIO_G3_Second_Gate_Reg;
372  break;
373  default:
374  BUG();
375  break;
376  }
377  return 0;
378 }
379 
380 static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
381 {
382  switch (counter_index) {
383  case 0:
384  return NITIO_G0_DMA_Config_Reg;
385  break;
386  case 1:
387  return NITIO_G1_DMA_Config_Reg;
388  break;
389  case 2:
390  return NITIO_G2_DMA_Config_Reg;
391  break;
392  case 3:
393  return NITIO_G3_DMA_Config_Reg;
394  break;
395  default:
396  BUG();
397  break;
398  }
399  return 0;
400 }
401 
402 static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
403 {
404  switch (counter_index) {
405  case 0:
406  return NITIO_G0_DMA_Status_Reg;
407  break;
408  case 1:
409  return NITIO_G1_DMA_Status_Reg;
410  break;
411  case 2:
412  return NITIO_G2_DMA_Status_Reg;
413  break;
414  case 3:
415  return NITIO_G3_DMA_Status_Reg;
416  break;
417  default:
418  BUG();
419  break;
420  }
421  return 0;
422 }
423 
424 static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
425 {
426  switch (counter_index) {
427  case 0:
428  return NITIO_G0_ABZ_Reg;
429  break;
430  case 1:
431  return NITIO_G1_ABZ_Reg;
432  break;
433  default:
434  BUG();
435  break;
436  }
437  return 0;
438 }
439 
440 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(int
441  counter_index)
442 {
443  switch (counter_index) {
444  case 0:
445  return NITIO_G0_Interrupt_Acknowledge_Reg;
446  break;
447  case 1:
448  return NITIO_G1_Interrupt_Acknowledge_Reg;
449  break;
450  case 2:
451  return NITIO_G2_Interrupt_Acknowledge_Reg;
452  break;
453  case 3:
454  return NITIO_G3_Interrupt_Acknowledge_Reg;
455  break;
456  default:
457  BUG();
458  break;
459  }
460  return 0;
461 }
462 
463 static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
464 {
465  switch (counter_index) {
466  case 0:
467  return NITIO_G0_Status_Reg;
468  break;
469  case 1:
470  return NITIO_G1_Status_Reg;
471  break;
472  case 2:
473  return NITIO_G2_Status_Reg;
474  break;
475  case 3:
476  return NITIO_G3_Status_Reg;
477  break;
478  default:
479  BUG();
480  break;
481  }
482  return 0;
483 }
484 
485 static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(int
486  counter_index)
487 {
488  switch (counter_index) {
489  case 0:
490  return NITIO_G0_Interrupt_Enable_Reg;
491  break;
492  case 1:
493  return NITIO_G1_Interrupt_Enable_Reg;
494  break;
495  case 2:
496  return NITIO_G2_Interrupt_Enable_Reg;
497  break;
498  case 3:
499  return NITIO_G3_Interrupt_Enable_Reg;
500  break;
501  default:
502  BUG();
503  break;
504  }
505  return 0;
506 }
507 
508 enum ni_gpct_variant {
509  ni_gpct_variant_e_series,
510  ni_gpct_variant_m_series,
511  ni_gpct_variant_660x
512 };
513 
514 struct ni_gpct {
515  struct ni_gpct_device *counter_dev;
516  unsigned counter_index;
517  unsigned chip_index;
518  uint64_t clock_period_ps; /* clock period in picoseconds */
519  struct mite_channel *mite_chan;
520  a4l_lock_t lock;
521 };
522 
523 struct ni_gpct_device {
524  a4l_dev_t *dev;
525  void (*write_register)(struct ni_gpct * counter,
526  unsigned int bits, enum ni_gpct_register reg);
527  unsigned (*read_register)(struct ni_gpct * counter,
528  enum ni_gpct_register reg);
529  enum ni_gpct_variant variant;
530  struct ni_gpct **counters;
531  unsigned num_counters;
532  unsigned regs[NITIO_Num_Registers];
533  a4l_lock_t regs_lock;
534 };
535 
536 #define Gi_Auto_Increment_Mask 0xff
537 #define Gi_Up_Down_Shift 5
538 
539 #define Gi_Arm_Bit 0x1
540 #define Gi_Save_Trace_Bit 0x2
541 #define Gi_Load_Bit 0x4
542 #define Gi_Disarm_Bit 0x10
543 #define Gi_Up_Down_Mask (0x3 << Gi_Up_Down_Shift)
544 #define Gi_Always_Down_Bits (0x0 << Gi_Up_Down_Shift)
545 #define Gi_Always_Up_Bits (0x1 << Gi_Up_Down_Shift)
546 #define Gi_Up_Down_Hardware_IO_Bits (0x2 << Gi_Up_Down_Shift)
547 #define Gi_Up_Down_Hardware_Gate_Bits (0x3 << Gi_Up_Down_Shift)
548 #define Gi_Write_Switch_Bit 0x80
549 #define Gi_Synchronize_Gate_Bit 0x100
550 #define Gi_Little_Big_Endian_Bit 0x200
551 #define Gi_Bank_Switch_Start_Bit 0x400
552 #define Gi_Bank_Switch_Mode_Bit 0x800
553 #define Gi_Bank_Switch_Enable_Bit 0x1000
554 #define Gi_Arm_Copy_Bit 0x2000
555 #define Gi_Save_Trace_Copy_Bit 0x4000
556 #define Gi_Disarm_Copy_Bit 0x8000
557 
558 #define Gi_Index_Phase_Bitshift 5
559 #define Gi_HW_Arm_Select_Shift 8
560 
561 #define Gi_Counting_Mode_Mask 0x7
562 #define Gi_Counting_Mode_Normal_Bits 0x0
563 #define Gi_Counting_Mode_QuadratureX1_Bits 0x1
564 #define Gi_Counting_Mode_QuadratureX2_Bits 0x2
565 #define Gi_Counting_Mode_QuadratureX4_Bits 0x3
566 #define Gi_Counting_Mode_Two_Pulse_Bits 0x4
567 #define Gi_Counting_Mode_Sync_Source_Bits 0x6
568 #define Gi_Index_Mode_Bit 0x10
569 #define Gi_Index_Phase_Mask (0x3 << Gi_Index_Phase_Bitshift)
570 #define Gi_Index_Phase_LowA_LowB (0x0 << Gi_Index_Phase_Bitshift)
571 #define Gi_Index_Phase_LowA_HighB (0x1 << Gi_Index_Phase_Bitshift)
572 #define Gi_Index_Phase_HighA_LowB (0x2 << Gi_Index_Phase_Bitshift)
573 #define Gi_Index_Phase_HighA_HighB (0x3 << Gi_Index_Phase_Bitshift)
574 
575 /* From m-series example code,
576  not documented in 660x register level manual */
577 #define Gi_HW_Arm_Enable_Bit 0x80
578 /* From m-series example code,
579  not documented in 660x register level manual */
580 #define Gi_660x_HW_Arm_Select_Mask (0x7 << Gi_HW_Arm_Select_Shift)
581 #define Gi_660x_Prescale_X8_Bit 0x1000
582 #define Gi_M_Series_Prescale_X8_Bit 0x2000
583 #define Gi_M_Series_HW_Arm_Select_Mask (0x1f << Gi_HW_Arm_Select_Shift)
584 /* Must be set for clocks over 40MHz,
585  which includes synchronous counting and quadrature modes */
586 #define Gi_660x_Alternate_Sync_Bit 0x2000
587 #define Gi_M_Series_Alternate_Sync_Bit 0x4000
588 /* From m-series example code,
589  not documented in 660x register level manual */
590 #define Gi_660x_Prescale_X2_Bit 0x4000
591 #define Gi_M_Series_Prescale_X2_Bit 0x8000
592 
593 static inline unsigned int Gi_Alternate_Sync_Bit(enum ni_gpct_variant variant)
594 {
595  switch (variant) {
596  case ni_gpct_variant_e_series:
597  return 0;
598  break;
599  case ni_gpct_variant_m_series:
600  return Gi_M_Series_Alternate_Sync_Bit;
601  break;
602  case ni_gpct_variant_660x:
603  return Gi_660x_Alternate_Sync_Bit;
604  break;
605  default:
606  BUG();
607  break;
608  }
609  return 0;
610 }
611 
612 static inline unsigned int Gi_Prescale_X2_Bit(enum ni_gpct_variant variant)
613 {
614  switch (variant) {
615  case ni_gpct_variant_e_series:
616  return 0;
617  break;
618  case ni_gpct_variant_m_series:
619  return Gi_M_Series_Prescale_X2_Bit;
620  break;
621  case ni_gpct_variant_660x:
622  return Gi_660x_Prescale_X2_Bit;
623  break;
624  default:
625  BUG();
626  break;
627  }
628  return 0;
629 }
630 
631 static inline unsigned int Gi_Prescale_X8_Bit(enum ni_gpct_variant variant)
632 {
633  switch (variant) {
634  case ni_gpct_variant_e_series:
635  return 0;
636  break;
637  case ni_gpct_variant_m_series:
638  return Gi_M_Series_Prescale_X8_Bit;
639  break;
640  case ni_gpct_variant_660x:
641  return Gi_660x_Prescale_X8_Bit;
642  break;
643  default:
644  BUG();
645  break;
646  }
647  return 0;
648 }
649 
650 static inline unsigned int Gi_HW_Arm_Select_Mask(enum ni_gpct_variant variant)
651 {
652  switch (variant) {
653  case ni_gpct_variant_e_series:
654  return 0;
655  break;
656  case ni_gpct_variant_m_series:
657  return Gi_M_Series_HW_Arm_Select_Mask;
658  break;
659  case ni_gpct_variant_660x:
660  return Gi_660x_HW_Arm_Select_Mask;
661  break;
662  default:
663  BUG();
664  break;
665  }
666  return 0;
667 }
668 
669 #define NI_660x_Timebase_1_Clock 0x0 /* 20MHz */
670 #define NI_660x_Source_Pin_i_Clock 0x1
671 #define NI_660x_Next_Gate_Clock 0xa
672 #define NI_660x_Timebase_2_Clock 0x12 /* 100KHz */
673 #define NI_660x_Next_TC_Clock 0x13
674 #define NI_660x_Timebase_3_Clock 0x1e /* 80MHz */
675 #define NI_660x_Logic_Low_Clock 0x1f
676 
677 #define ni_660x_max_rtsi_channel 6
678 #define ni_660x_max_source_pin 7
679 
680 static inline unsigned int NI_660x_RTSI_Clock(unsigned int n)
681 {
682  BUG_ON(n > ni_660x_max_rtsi_channel);
683  return (0xb + n);
684 }
685 
686 static inline unsigned int NI_660x_Source_Pin_Clock(unsigned int n)
687 {
688  BUG_ON(n > ni_660x_max_source_pin);
689  return (0x2 + n);
690 }
691 
692 /* Clock sources for ni e and m series boards,
693  get bits with Gi_Source_Select_Bits() */
694 #define NI_M_Series_Timebase_1_Clock 0x0 /* 20MHz */
695 #define NI_M_Series_Timebase_2_Clock 0x12 /* 100KHz */
696 #define NI_M_Series_Next_TC_Clock 0x13
697 #define NI_M_Series_Next_Gate_Clock 0x14 /* when Gi_Src_SubSelect = 0 */
698 #define NI_M_Series_PXI_Star_Trigger_Clock 0x14 /* when Gi_Src_SubSelect = 1 */
699 #define NI_M_Series_PXI10_Clock 0x1d
700 #define NI_M_Series_Timebase_3_Clock 0x1e /* 80MHz, when Gi_Src_SubSelect = 0 */
701 #define NI_M_Series_Analog_Trigger_Out_Clock 0x1e /* when Gi_Src_SubSelect = 1 */
702 #define NI_M_Series_Logic_Low_Clock 0x1f
703 
704 #define ni_m_series_max_pfi_channel 15
705 #define ni_m_series_max_rtsi_channel 7
706 
707 static inline unsigned int NI_M_Series_PFI_Clock(unsigned int n)
708 {
709  BUG_ON(n > ni_m_series_max_pfi_channel);
710  if (n < 10)
711  return 1 + n;
712  else
713  return 0xb + n;
714 }
715 
716 static inline unsigned int NI_M_Series_RTSI_Clock(unsigned int n)
717 {
718  BUG_ON(n > ni_m_series_max_rtsi_channel);
719  if (n == 7)
720  return 0x1b;
721  else
722  return 0xb + n;
723 }
724 
725 #define NI_660x_Source_Pin_i_Gate_Select 0x0
726 #define NI_660x_Gate_Pin_i_Gate_Select 0x1
727 #define NI_660x_Next_SRC_Gate_Select 0xa
728 #define NI_660x_Next_Out_Gate_Select 0x14
729 #define NI_660x_Logic_Low_Gate_Select 0x1f
730 #define ni_660x_max_gate_pin 7
731 
732 static inline unsigned int NI_660x_Gate_Pin_Gate_Select(unsigned int n)
733 {
734  BUG_ON(n > ni_660x_max_gate_pin);
735  return 0x2 + n;
736 }
737 
738 static inline unsigned int NI_660x_RTSI_Gate_Select(unsigned int n)
739 {
740  BUG_ON(n > ni_660x_max_rtsi_channel);
741  return 0xb + n;
742 }
743 
744 
745 #define NI_M_Series_Timestamp_Mux_Gate_Select 0x0
746 #define NI_M_Series_AI_START2_Gate_Select 0x12
747 #define NI_M_Series_PXI_Star_Trigger_Gate_Select 0x13
748 #define NI_M_Series_Next_Out_Gate_Select 0x14
749 #define NI_M_Series_AI_START1_Gate_Select 0x1c
750 #define NI_M_Series_Next_SRC_Gate_Select 0x1d
751 #define NI_M_Series_Analog_Trigger_Out_Gate_Select 0x1e
752 #define NI_M_Series_Logic_Low_Gate_Select 0x1f
753 
754 static inline unsigned int NI_M_Series_RTSI_Gate_Select(unsigned int n)
755 {
756  BUG_ON(n > ni_m_series_max_rtsi_channel);
757  if (n == 7)
758  return 0x1b;
759  return 0xb + n;
760 }
761 
762 static inline unsigned int NI_M_Series_PFI_Gate_Select(unsigned int n)
763 {
764  BUG_ON(n > ni_m_series_max_pfi_channel);
765  if (n < 10)
766  return 1 + n;
767  return 0xb + n;
768 }
769 
770 
771 #define Gi_Source_Select_Shift 2
772 #define Gi_Gate_Select_Shift 7
773 
774 #define Gi_Read_Acknowledges_Irq 0x1 /* not present on 660x */
775 #define Gi_Write_Acknowledges_Irq 0x2 /* not present on 660x */
776 #define Gi_Source_Select_Mask 0x7c
777 #define Gi_Gate_Select_Mask (0x1f << Gi_Gate_Select_Shift)
778 #define Gi_Gate_Select_Load_Source_Bit 0x1000
779 #define Gi_Or_Gate_Bit 0x2000
780 #define Gi_Output_Polarity_Bit 0x4000 /* set to invert */
781 #define Gi_Source_Polarity_Bit 0x8000 /* set to invert */
782 
783 #define Gi_Source_Select_Bits(x) ((x << Gi_Source_Select_Shift) & \
784  Gi_Source_Select_Mask)
785 #define Gi_Gate_Select_Bits(x) ((x << Gi_Gate_Select_Shift) & \
786  Gi_Gate_Select_Mask)
787 
788 #define Gi_Gating_Mode_Mask 0x3
789 #define Gi_Gating_Disabled_Bits 0x0
790 #define Gi_Level_Gating_Bits 0x1
791 #define Gi_Rising_Edge_Gating_Bits 0x2
792 #define Gi_Falling_Edge_Gating_Bits 0x3
793 #define Gi_Gate_On_Both_Edges_Bit 0x4 /* used in conjunction with
794  rising edge gating mode */
795 #define Gi_Trigger_Mode_for_Edge_Gate_Mask 0x18
796 #define Gi_Edge_Gate_Starts_Stops_Bits 0x0
797 #define Gi_Edge_Gate_Stops_Starts_Bits 0x8
798 #define Gi_Edge_Gate_Starts_Bits 0x10
799 #define Gi_Edge_Gate_No_Starts_or_Stops_Bits 0x18
800 #define Gi_Stop_Mode_Mask 0x60
801 #define Gi_Stop_on_Gate_Bits 0x00
802 #define Gi_Stop_on_Gate_or_TC_Bits 0x20
803 #define Gi_Stop_on_Gate_or_Second_TC_Bits 0x40
804 #define Gi_Load_Source_Select_Bit 0x80
805 #define Gi_Output_Mode_Mask 0x300
806 #define Gi_Output_TC_Pulse_Bits 0x100
807 #define Gi_Output_TC_Toggle_Bits 0x200
808 #define Gi_Output_TC_or_Gate_Toggle_Bits 0x300
809 #define Gi_Counting_Once_Mask 0xc00
810 #define Gi_No_Hardware_Disarm_Bits 0x000
811 #define Gi_Disarm_at_TC_Bits 0x400
812 #define Gi_Disarm_at_Gate_Bits 0x800
813 #define Gi_Disarm_at_TC_or_Gate_Bits 0xc00
814 #define Gi_Loading_On_TC_Bit 0x1000
815 #define Gi_Gate_Polarity_Bit 0x2000
816 #define Gi_Loading_On_Gate_Bit 0x4000
817 #define Gi_Reload_Source_Switching_Bit 0x8000
818 
819 #define NI_660x_Source_Pin_i_Second_Gate_Select 0x0
820 #define NI_660x_Up_Down_Pin_i_Second_Gate_Select 0x1
821 #define NI_660x_Next_SRC_Second_Gate_Select 0xa
822 #define NI_660x_Next_Out_Second_Gate_Select 0x14
823 #define NI_660x_Selected_Gate_Second_Gate_Select 0x1e
824 #define NI_660x_Logic_Low_Second_Gate_Select 0x1f
825 
826 #define ni_660x_max_up_down_pin 7
827 
828 static inline
829 unsigned int NI_660x_Up_Down_Pin_Second_Gate_Select(unsigned int n)
830 {
831  BUG_ON(n > ni_660x_max_up_down_pin);
832  return 0x2 + n;
833 }
834 static inline
835 unsigned int NI_660x_RTSI_Second_Gate_Select(unsigned int n)
836 {
837  BUG_ON(n > ni_660x_max_rtsi_channel);
838  return 0xb + n;
839 }
840 
841 #define Gi_Second_Gate_Select_Shift 7
842 
843 /*FIXME: m-series has a second gate subselect bit */
844 /*FIXME: m-series second gate sources are undocumented (by NI)*/
845 #define Gi_Second_Gate_Mode_Bit 0x1
846 #define Gi_Second_Gate_Select_Mask (0x1f << Gi_Second_Gate_Select_Shift)
847 #define Gi_Second_Gate_Polarity_Bit 0x2000
848 #define Gi_Second_Gate_Subselect_Bit 0x4000 /* m-series only */
849 #define Gi_Source_Subselect_Bit 0x8000 /* m-series only */
850 
851 static inline
852 unsigned int Gi_Second_Gate_Select_Bits(unsigned int second_gate_select)
853 {
854  return (second_gate_select << Gi_Second_Gate_Select_Shift) &
855  Gi_Second_Gate_Select_Mask;
856 }
857 
858 #define G0_Save_Bit 0x1
859 #define G1_Save_Bit 0x2
860 #define G0_Counting_Bit 0x4
861 #define G1_Counting_Bit 0x8
862 #define G0_Next_Load_Source_Bit 0x10
863 #define G1_Next_Load_Source_Bit 0x20
864 #define G0_Stale_Data_Bit 0x40
865 #define G1_Stale_Data_Bit 0x80
866 #define G0_Armed_Bit 0x100
867 #define G1_Armed_Bit 0x200
868 #define G0_No_Load_Between_Gates_Bit 0x400
869 #define G1_No_Load_Between_Gates_Bit 0x800
870 #define G0_TC_Error_Bit 0x1000
871 #define G1_TC_Error_Bit 0x2000
872 #define G0_Gate_Error_Bit 0x4000
873 #define G1_Gate_Error_Bit 0x8000
874 
875 static inline unsigned int Gi_Counting_Bit(unsigned int counter_index)
876 {
877  if (counter_index % 2)
878  return G1_Counting_Bit;
879  return G0_Counting_Bit;
880 }
881 
882 static inline unsigned int Gi_Armed_Bit(unsigned int counter_index)
883 {
884  if (counter_index % 2)
885  return G1_Armed_Bit;
886  return G0_Armed_Bit;
887 }
888 
889 static inline unsigned int Gi_Next_Load_Source_Bit(unsigned counter_index)
890 {
891  if (counter_index % 2)
892  return G1_Next_Load_Source_Bit;
893  return G0_Next_Load_Source_Bit;
894 }
895 
896 static inline unsigned int Gi_Stale_Data_Bit(unsigned int counter_index)
897 {
898  if (counter_index % 2)
899  return G1_Stale_Data_Bit;
900  return G0_Stale_Data_Bit;
901 }
902 
903 static inline unsigned int Gi_TC_Error_Bit(unsigned int counter_index)
904 {
905  if (counter_index % 2)
906  return G1_TC_Error_Bit;
907  return G0_TC_Error_Bit;
908 }
909 
910 static inline unsigned int Gi_Gate_Error_Bit(unsigned int counter_index)
911 {
912  if (counter_index % 2)
913  return G1_Gate_Error_Bit;
914  return G0_Gate_Error_Bit;
915 }
916 
917 /* Joint reset register bits */
918 static inline unsigned Gi_Reset_Bit(unsigned int counter_index)
919 {
920  return 0x1 << (2 + (counter_index % 2));
921 }
922 
923 #define G0_Output_Bit 0x1
924 #define G1_Output_Bit 0x2
925 #define G0_HW_Save_Bit 0x1000
926 #define G1_HW_Save_Bit 0x2000
927 #define G0_Permanent_Stale_Bit 0x4000
928 #define G1_Permanent_Stale_Bit 0x8000
929 
930 static inline unsigned int Gi_Permanent_Stale_Bit(unsigned
931  counter_index)
932 {
933  if (counter_index % 2)
934  return G1_Permanent_Stale_Bit;
935  return G0_Permanent_Stale_Bit;
936 }
937 
938 #define Gi_DMA_Enable_Bit 0x1
939 #define Gi_DMA_Write_Bit 0x2
940 #define Gi_DMA_Int_Bit 0x4
941 
942 #define Gi_DMA_Readbank_Bit 0x2000
943 #define Gi_DRQ_Error_Bit 0x4000
944 #define Gi_DRQ_Status_Bit 0x8000
945 
946 #define G0_Gate_Error_Confirm_Bit 0x20
947 #define G0_TC_Error_Confirm_Bit 0x40
948 
949 #define G1_Gate_Error_Confirm_Bit 0x2
950 #define G1_TC_Error_Confirm_Bit 0x4
951 
952 static inline unsigned int Gi_Gate_Error_Confirm_Bit(unsigned int counter_index)
953 {
954  if (counter_index % 2)
955  return G1_Gate_Error_Confirm_Bit;
956  return G0_Gate_Error_Confirm_Bit;
957 }
958 
959 static inline unsigned int Gi_TC_Error_Confirm_Bit(unsigned int counter_index)
960 {
961  if (counter_index % 2)
962  return G1_TC_Error_Confirm_Bit;
963  return G0_TC_Error_Confirm_Bit;
964 }
965 
966 /* Bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
967 #define Gi_TC_Interrupt_Ack_Bit 0x4000
968 #define Gi_Gate_Interrupt_Ack_Bit 0x8000
969 
970 #define Gi_Gate_Interrupt_Bit 0x4
971 #define Gi_TC_Bit 0x8
972 #define Gi_Interrupt_Bit 0x8000
973 
974 #define G0_TC_Interrupt_Enable_Bit 0x40
975 #define G0_Gate_Interrupt_Enable_Bit 0x100
976 
977 #define G1_TC_Interrupt_Enable_Bit 0x200
978 #define G1_Gate_Interrupt_Enable_Bit 0x400
979 
980 static inline unsigned int Gi_Gate_Interrupt_Enable_Bit(unsigned int counter_index)
981 {
982  unsigned int bit;
983 
984  if (counter_index % 2) {
985  bit = G1_Gate_Interrupt_Enable_Bit;
986  } else {
987  bit = G0_Gate_Interrupt_Enable_Bit;
988  }
989  return bit;
990 }
991 
992 #define counter_status_mask (A4L_COUNTER_ARMED | A4L_COUNTER_COUNTING)
993 
994 #define NI_USUAL_PFI_SELECT(x) ((x < 10) ? (0x1 + x) : (0xb + x))
995 #define NI_USUAL_RTSI_SELECT(x) ((x < 7 ) ? (0xb + x) : (0x1b + x))
996 
997 /* Mode bits for NI general-purpose counters, set with
998  INSN_CONFIG_SET_COUNTER_MODE */
999 #define NI_GPCT_COUNTING_MODE_SHIFT 16
1000 #define NI_GPCT_INDEX_PHASE_BITSHIFT 20
1001 #define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
1002 
1003 #define NI_GPCT_GATE_ON_BOTH_EDGES_BIT 0x4
1004 #define NI_GPCT_EDGE_GATE_MODE_MASK 0x18
1005 #define NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS 0x0
1006 #define NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS 0x8
1007 #define NI_GPCT_EDGE_GATE_STARTS_BITS 0x10
1008 #define NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS 0x18
1009 #define NI_GPCT_STOP_MODE_MASK 0x60
1010 #define NI_GPCT_STOP_ON_GATE_BITS 0x00
1011 #define NI_GPCT_STOP_ON_GATE_OR_TC_BITS 0x20
1012 #define NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS 0x40
1013 #define NI_GPCT_LOAD_B_SELECT_BIT 0x80
1014 #define NI_GPCT_OUTPUT_MODE_MASK 0x300
1015 #define NI_GPCT_OUTPUT_TC_PULSE_BITS 0x100
1016 #define NI_GPCT_OUTPUT_TC_TOGGLE_BITS 0x200
1017 #define NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS 0x300
1018 #define NI_GPCT_HARDWARE_DISARM_MASK 0xc00
1019 #define NI_GPCT_NO_HARDWARE_DISARM_BITS 0x000
1020 #define NI_GPCT_DISARM_AT_TC_BITS 0x400
1021 #define NI_GPCT_DISARM_AT_GATE_BITS 0x800
1022 #define NI_GPCT_DISARM_AT_TC_OR_GATE_BITS 0xc00
1023 #define NI_GPCT_LOADING_ON_TC_BIT 0x1000
1024 #define NI_GPCT_LOADING_ON_GATE_BIT 0x4000
1025 #define NI_GPCT_COUNTING_MODE_MASK 0x7 << NI_GPCT_COUNTING_MODE_SHIFT
1026 #define NI_GPCT_COUNTING_MODE_NORMAL_BITS 0x0 << NI_GPCT_COUNTING_MODE_SHIFT
1027 #define NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS 0x1 << NI_GPCT_COUNTING_MODE_SHIFT
1028 #define NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS 0x2 << NI_GPCT_COUNTING_MODE_SHIFT
1029 #define NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS 0x3 << NI_GPCT_COUNTING_MODE_SHIFT
1030 #define NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS 0x4 << NI_GPCT_COUNTING_MODE_SHIFT
1031 #define NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS 0x6 << NI_GPCT_COUNTING_MODE_SHIFT
1032 #define NI_GPCT_INDEX_PHASE_MASK 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT
1033 #define NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS 0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT
1034 #define NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS 0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT
1035 #define NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS 0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT
1036 #define NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT
1037 #define NI_GPCT_INDEX_ENABLE_BIT 0x400000
1038 #define NI_GPCT_COUNTING_DIRECTION_MASK 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1039 #define NI_GPCT_COUNTING_DIRECTION_DOWN_BITS 0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1040 #define NI_GPCT_COUNTING_DIRECTION_UP_BITS 0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1041 #define NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS 0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1042 #define NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS 0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT
1043 #define NI_GPCT_RELOAD_SOURCE_MASK 0xc000000
1044 #define NI_GPCT_RELOAD_SOURCE_FIXED_BITS 0x0
1045 #define NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS 0x4000000
1046 #define NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS 0x8000000
1047 #define NI_GPCT_OR_GATE_BIT 0x10000000
1048 #define NI_GPCT_INVERT_OUTPUT_BIT 0x20000000
1049 
1050 /* Bits for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC when
1051  using NI general-purpose counters. */
1052 #define NI_GPCT_CLOCK_SRC_SELECT_MASK 0x3f
1053 #define NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS 0x0
1054 #define NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS 0x1
1055 #define NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS 0x2
1056 #define NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS 0x3
1057 #define NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS 0x4
1058 #define NI_GPCT_NEXT_TC_CLOCK_SRC_BITS 0x5
1059 #define NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS 0x6 /* NI 660x-specific */
1060 #define NI_GPCT_PXI10_CLOCK_SRC_BITS 0x7
1061 #define NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS 0x8
1062 #define NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS 0x9
1063 #define NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK 0x30000000
1064 #define NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS 0x0
1065 #define NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS 0x10000000 /* divide source by 2 */
1066 #define NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS 0x20000000 /* divide source by 8 */
1067 #define NI_GPCT_INVERT_CLOCK_SRC_BIT 0x80000000
1068 #define NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(x) (0x10 + x)
1069 #define NI_GPCT_RTSI_CLOCK_SRC_BITS(x) (0x18 + x)
1070 #define NI_GPCT_PFI_CLOCK_SRC_BITS(x) (0x20 + x)
1071 
1072 /* Possibilities for setting a gate source with
1073  INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
1074  May be bitwise-or'd with CR_EDGE or CR_INVERT. */
1075 /* M-series gates */
1076 #define NI_GPCT_TIMESTAMP_MUX_GATE_SELECT 0x0
1077 #define NI_GPCT_AI_START2_GATE_SELECT 0x12
1078 #define NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT 0x13
1079 #define NI_GPCT_NEXT_OUT_GATE_SELECT 0x14
1080 #define NI_GPCT_AI_START1_GATE_SELECT 0x1c
1081 #define NI_GPCT_NEXT_SOURCE_GATE_SELECT 0x1d
1082 #define NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT 0x1e
1083 #define NI_GPCT_LOGIC_LOW_GATE_SELECT 0x1f
1084 /* More gates for 660x */
1085 #define NI_GPCT_SOURCE_PIN_i_GATE_SELECT 0x100
1086 #define NI_GPCT_GATE_PIN_i_GATE_SELECT 0x101
1087 /* More gates for 660x "second gate" */
1088 #define NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT 0x201
1089 #define NI_GPCT_SELECTED_GATE_GATE_SELECT 0x21e
1090 /* M-series "second gate" sources are unknown, we should add them here
1091  with an offset of 0x300 when known. */
1092 #define NI_GPCT_DISABLED_GATE_SELECT 0x8000
1093 #define NI_GPCT_GATE_PIN_GATE_SELECT(x) (0x102 + x)
1094 #define NI_GPCT_RTSI_GATE_SELECT(x) NI_USUAL_RTSI_SELECT(x)
1095 #define NI_GPCT_PFI_GATE_SELECT(x) NI_USUAL_PFI_SELECT(x)
1096 #define NI_GPCT_UP_DOWN_PIN_GATE_SELECT(x) (0x202 + x)
1097 
1098 /* Possibilities for setting a source with INSN_CONFIG_SET_OTHER_SRC
1099  when using NI general-purpose counters. */
1100 #define NI_GPCT_SOURCE_ENCODER_A 0
1101 #define NI_GPCT_SOURCE_ENCODER_B 1
1102 #define NI_GPCT_SOURCE_ENCODER_Z 2
1103 /* M-series gates */
1104 /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
1105 #define NI_GPCT_DISABLED_OTHER_SELECT 0x8000
1106 #define NI_GPCT_PFI_OTHER_SELECT(x) NI_USUAL_PFI_SELECT(x)
1107 
1108 /* Start sources for ni general-purpose counters for use with
1109  INSN_CONFIG_ARM */
1110 #define NI_GPCT_ARM_IMMEDIATE 0x0
1111 /* Start both the counter and the adjacent paired counter
1112  simultaneously */
1113 #define NI_GPCT_ARM_PAIRED_IMMEDIATE 0x1
1114 /* NI doesn't document bits for selecting hardware arm triggers. If
1115  the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least significant
1116  bits (3 bits for 660x or 5 bits for m-series) through to the
1117  hardware. This will at least allow someone to figure out what the bits
1118  do later. */
1119 #define NI_GPCT_ARM_UNKNOWN 0x1000
1120 
1121 /* Digital filtering options for ni 660x for use with
1122  INSN_CONFIG_FILTER. */
1123 #define NI_GPCT_FILTER_OFF 0x0
1124 #define NI_GPCT_FILTER_TIMEBASE_3_SYNC 0x1
1125 #define NI_GPCT_FILTER_100x_TIMEBASE_1 0x2
1126 #define NI_GPCT_FILTER_20x_TIMEBASE_1 0x3
1127 #define NI_GPCT_FILTER_10x_TIMEBASE_1 0x4
1128 #define NI_GPCT_FILTER_2x_TIMEBASE_1 0x5
1129 #define NI_GPCT_FILTER_2x_TIMEBASE_3 0x6
1130 
1131 /* Master clock sources for ni mio boards and
1132  INSN_CONFIG_SET_CLOCK_SRC */
1133 #define NI_MIO_INTERNAL_CLOCK 0
1134 #define NI_MIO_RTSI_CLOCK 1
1135 /* Doesn't work for m-series, use NI_MIO_PLL_RTSI_CLOCK() the
1136  NI_MIO_PLL_* sources are m-series only */
1137 #define NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK 2
1138 #define NI_MIO_PLL_PXI10_CLOCK 3
1139 #define NI_MIO_PLL_RTSI0_CLOCK 4
1140 
1141 #define NI_MIO_PLL_RTSI_CLOCK(x) (NI_MIO_PLL_RTSI0_CLOCK + (x))
1142 
1143 /* Signals which can be routed to an NI RTSI pin with
1144  INSN_CONFIG_SET_ROUTING. The numbers assigned are not arbitrary, they
1145  correspond to the bits required to program the board. */
1146 #define NI_RTSI_OUTPUT_ADR_START1 0
1147 #define NI_RTSI_OUTPUT_ADR_START2 1
1148 #define NI_RTSI_OUTPUT_SCLKG 2
1149 #define NI_RTSI_OUTPUT_DACUPDN 3
1150 #define NI_RTSI_OUTPUT_DA_START1 4
1151 #define NI_RTSI_OUTPUT_G_SRC0 5
1152 #define NI_RTSI_OUTPUT_G_GATE0 6
1153 #define NI_RTSI_OUTPUT_RGOUT0 7
1154 #define NI_RTSI_OUTPUT_RTSI_BRD_0 8
1155 /* Pre-m-series always have RTSI clock on line 7 */
1156 #define NI_RTSI_OUTPUT_RTSI_OSC 12
1157 
1158 #define NI_RTSI_OUTPUT_RTSI_BRD(x) (NI_RTSI_OUTPUT_RTSI_BRD_0 + (x))
1159 
1160 
1161 int a4l_ni_tio_rinsn(struct ni_gpct *counter, a4l_kinsn_t *insn);
1162 int a4l_ni_tio_winsn(struct ni_gpct *counter, a4l_kinsn_t *insn);
1163 int a4l_ni_tio_insn_config(struct ni_gpct *counter, a4l_kinsn_t *insn);
1164 void a4l_ni_tio_init_counter(struct ni_gpct *counter);
1165 
1166 struct ni_gpct_device *a4l_ni_gpct_device_construct(a4l_dev_t * dev,
1167  void (*write_register) (struct ni_gpct * counter, unsigned int bits,
1168  enum ni_gpct_register reg),
1169  unsigned int (*read_register) (struct ni_gpct * counter,
1170  enum ni_gpct_register reg), enum ni_gpct_variant variant,
1171  unsigned int num_counters);
1172 void a4l_ni_gpct_device_destroy(struct ni_gpct_device *counter_dev);
1173 
1174 #if (defined(CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE) || \
1175  defined(CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE_MODULE))
1176 
1177 extern a4l_cmd_t a4l_ni_tio_cmd_mask;
1178 
1179 int a4l_ni_tio_input_inttrig(struct ni_gpct *counter, lsampl_t trignum);
1180 int a4l_ni_tio_cmd(struct ni_gpct *counter, a4l_cmd_t *cmd);
1181 int a4l_ni_tio_cmdtest(struct ni_gpct *counter, a4l_cmd_t *cmd);
1182 int a4l_ni_tio_cancel(struct ni_gpct *counter);
1183 
1184 void a4l_ni_tio_handle_interrupt(struct ni_gpct *counter, a4l_dev_t *dev);
1185 void a4l_ni_tio_set_mite_channel(struct ni_gpct *counter,
1186  struct mite_channel *mite_chan);
1187 void a4l_ni_tio_acknowledge_and_confirm(struct ni_gpct *counter,
1188  int *gate_error,
1189  int *tc_error,
1190  int *perm_stale_data, int *stale_data);
1191 
1192 #endif /* CONFIG_XENO_DRIVERS_ANALOGY_NI_MITE */
1193 
1194 #endif /* !__ANALOGY_NI_TIO_H__ */
a4l_cmd_desc
Structure describing the asynchronous instruction.
Definition: command.h:198
analogy_driver.h
Analogy for Linux, driver facilities.
mite.h
Hardware driver for NI Mite PCI interface chip.