ksrc/drivers/analogy/national_instruments/ni_stc.h

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#ifndef __ANALOGY_NI_STC_H__
#define __ANALOGY_NI_STC_H__

#include "ni_tio.h"

#define _bit15          0x8000
#define _bit14          0x4000
#define _bit13          0x2000
#define _bit12          0x1000
#define _bit11          0x0800
#define _bit10          0x0400
#define _bit9           0x0200
#define _bit8           0x0100
#define _bit7           0x0080
#define _bit6           0x0040
#define _bit5           0x0020
#define _bit4           0x0010
#define _bit3           0x0008
#define _bit2           0x0004
#define _bit1           0x0002
#define _bit0           0x0001

#define NUM_PFI_OUTPUT_SELECT_REGS 6

/* Registers in the National Instruments DAQ-STC chip */

#define Interrupt_A_Ack_Register        2
#define G0_Gate_Interrupt_Ack                   _bit15
#define G0_TC_Interrupt_Ack                     _bit14
#define AI_Error_Interrupt_Ack                  _bit13
#define AI_STOP_Interrupt_Ack                   _bit12
#define AI_START_Interrupt_Ack                  _bit11
#define AI_START2_Interrupt_Ack                 _bit10
#define AI_START1_Interrupt_Ack                 _bit9
#define AI_SC_TC_Interrupt_Ack                  _bit8
#define AI_SC_TC_Error_Confirm                  _bit7
#define G0_TC_Error_Confirm                     _bit6
#define G0_Gate_Error_Confirm                   _bit5

#define AI_Status_1_Register            2
#define Interrupt_A_St                          _bit15
#define AI_FIFO_Full_St                         _bit14
#define AI_FIFO_Half_Full_St                    _bit13
#define AI_FIFO_Empty_St                        _bit12
#define AI_Overrun_St                           _bit11
#define AI_Overflow_St                          _bit10
#define AI_SC_TC_Error_St                       _bit9
#define AI_START2_St                            _bit8
#define AI_START1_St                            _bit7
#define AI_SC_TC_St                             _bit6
#define AI_START_St                             _bit5
#define AI_STOP_St                              _bit4
#define G0_TC_St                                _bit3
#define G0_Gate_Interrupt_St                    _bit2
#define AI_FIFO_Request_St                      _bit1
#define Pass_Thru_0_Interrupt_St                _bit0

#define AI_Status_2_Register            5

#define Interrupt_B_Ack_Register        3
#define G1_Gate_Error_Confirm                   _bit1
#define G1_TC_Error_Confirm                     _bit2
#define AO_BC_TC_Trigger_Error_Confirm          _bit3
#define AO_BC_TC_Error_Confirm                  _bit4
#define AO_UI2_TC_Error_Confrim                 _bit5
#define AO_UI2_TC_Interrupt_Ack                 _bit6
#define AO_UC_TC_Interrupt_Ack                  _bit7
#define AO_BC_TC_Interrupt_Ack                  _bit8
#define AO_START1_Interrupt_Ack                 _bit9
#define AO_UPDATE_Interrupt_Ack                 _bit10
#define AO_START_Interrupt_Ack                  _bit11
#define AO_STOP_Interrupt_Ack                   _bit12
#define AO_Error_Interrupt_Ack                  _bit13
#define G1_TC_Interrupt_Ack                     _bit14
#define G1_Gate_Interrupt_Ack                   _bit15

#define AO_Status_1_Register            3
#define Interrupt_B_St                          _bit15
#define AO_FIFO_Full_St                         _bit14
#define AO_FIFO_Half_Full_St                    _bit13
#define AO_FIFO_Empty_St                        _bit12
#define AO_BC_TC_Error_St                       _bit11
#define AO_START_St                             _bit10
#define AO_Overrun_St                           _bit9
#define AO_START1_St                            _bit8
#define AO_BC_TC_St                             _bit7
#define AO_UC_TC_St                             _bit6
#define AO_UPDATE_St                            _bit5
#define AO_UI2_TC_St                            _bit4
#define G1_TC_St                                _bit3
#define G1_Gate_Interrupt_St                    _bit2
#define AO_FIFO_Request_St                      _bit1
#define Pass_Thru_1_Interrupt_St                _bit0


#define AI_Command_2_Register           4
#define AI_End_On_SC_TC                         _bit15
#define AI_End_On_End_Of_Scan                   _bit14
#define AI_START1_Disable                       _bit11
#define AI_SC_Save_Trace                        _bit10
#define AI_SI_Switch_Load_On_SC_TC              _bit9
#define AI_SI_Switch_Load_On_STOP               _bit8
#define AI_SI_Switch_Load_On_TC                 _bit7
#define AI_SC_Switch_Load_On_TC                 _bit4
#define AI_STOP_Pulse                           _bit3
#define AI_START_Pulse                          _bit2
#define AI_START2_Pulse                         _bit1
#define AI_START1_Pulse                         _bit0

#define AO_Command_2_Register           5
#define AO_End_On_BC_TC(x)                      (((x) & 0x3) << 14)
#define AO_Start_Stop_Gate_Enable               _bit13
#define AO_UC_Save_Trace                        _bit12
#define AO_BC_Gate_Enable                       _bit11
#define AO_BC_Save_Trace                        _bit10
#define AO_UI_Switch_Load_On_BC_TC              _bit9
#define AO_UI_Switch_Load_On_Stop               _bit8
#define AO_UI_Switch_Load_On_TC                 _bit7
#define AO_UC_Switch_Load_On_BC_TC              _bit6
#define AO_UC_Switch_Load_On_TC                 _bit5
#define AO_BC_Switch_Load_On_TC                 _bit4
#define AO_Mute_B                               _bit3
#define AO_Mute_A                               _bit2
#define AO_UPDATE2_Pulse                        _bit1
#define AO_START1_Pulse                         _bit0

#define AO_Status_2_Register            6

#define DIO_Parallel_Input_Register     7

#define AI_Command_1_Register           8
#define AI_Analog_Trigger_Reset                 _bit14
#define AI_Disarm                               _bit13
#define AI_SI2_Arm                              _bit12
#define AI_SI2_Load                             _bit11
#define AI_SI_Arm                               _bit10
#define AI_SI_Load                              _bit9
#define AI_DIV_Arm                              _bit8
#define AI_DIV_Load                             _bit7
#define AI_SC_Arm                               _bit6
#define AI_SC_Load                              _bit5
#define AI_SCAN_IN_PROG_Pulse                   _bit4
#define AI_EXTMUX_CLK_Pulse                     _bit3
#define AI_LOCALMUX_CLK_Pulse                   _bit2
#define AI_SC_TC_Pulse                          _bit1
#define AI_CONVERT_Pulse                        _bit0

#define AO_Command_1_Register           9
#define AO_Analog_Trigger_Reset                 _bit15
#define AO_START_Pulse                          _bit14
#define AO_Disarm                               _bit13
#define AO_UI2_Arm_Disarm                       _bit12
#define AO_UI2_Load                             _bit11
#define AO_UI_Arm                               _bit10
#define AO_UI_Load                              _bit9
#define AO_UC_Arm                               _bit8
#define AO_UC_Load                              _bit7
#define AO_BC_Arm                               _bit6
#define AO_BC_Load                              _bit5
#define AO_DAC1_Update_Mode                     _bit4
#define AO_LDAC1_Source_Select                  _bit3
#define AO_DAC0_Update_Mode                     _bit2
#define AO_LDAC0_Source_Select                  _bit1
#define AO_UPDATE_Pulse                         _bit0


#define DIO_Output_Register             10
#define DIO_Parallel_Data_Out(a)                ((a)&0xff)
#define DIO_Parallel_Data_Mask                  0xff
#define DIO_SDOUT                               _bit0
#define DIO_SDIN                                _bit4
#define DIO_Serial_Data_Out(a)                  (((a)&0xff)<<8)
#define DIO_Serial_Data_Mask                    0xff00

#define DIO_Control_Register            11
#define DIO_Software_Serial_Control             _bit11
#define DIO_HW_Serial_Timebase                  _bit10
#define DIO_HW_Serial_Enable                    _bit9
#define DIO_HW_Serial_Start                     _bit8
#define DIO_Pins_Dir(a)                         ((a)&0xff)
#define DIO_Pins_Dir_Mask                       0xff

#define AI_Mode_1_Register              12
#define AI_CONVERT_Source_Select(a)             (((a) & 0x1f) << 11)
#define AI_SI_Source_select(a)                  (((a) & 0x1f) << 6)
#define AI_CONVERT_Source_Polarity              _bit5
#define AI_SI_Source_Polarity           _bit4
#define AI_Start_Stop                           _bit3
#define AI_Mode_1_Reserved                      _bit2
#define AI_Continuous                           _bit1
#define AI_Trigger_Once                         _bit0

#define AI_Mode_2_Register              13
#define AI_SC_Gate_Enable                       _bit15
#define AI_Start_Stop_Gate_Enable               _bit14
#define AI_Pre_Trigger                          _bit13
#define AI_External_MUX_Present                 _bit12
#define AI_SI2_Initial_Load_Source              _bit9
#define AI_SI2_Reload_Mode                      _bit8
#define AI_SI_Initial_Load_Source               _bit7
#define AI_SI_Reload_Mode(a)                    (((a) & 0x7)<<4)
#define AI_SI_Write_Switch                      _bit3
#define AI_SC_Initial_Load_Source               _bit2
#define AI_SC_Reload_Mode                       _bit1
#define AI_SC_Write_Switch                      _bit0

#define AI_SI_Load_A_Registers          14
#define AI_SI_Load_B_Registers          16
#define AI_SC_Load_A_Registers          18
#define AI_SC_Load_B_Registers          20
#define AI_SI_Save_Registers            64
#define AI_SC_Save_Registers            66

#define AI_SI2_Load_A_Register          23
#define AI_SI2_Load_B_Register          25

#define Joint_Status_1_Register         27
#define DIO_Serial_IO_In_Progress_St            _bit12

#define DIO_Serial_Input_Register       28
#define Joint_Status_2_Register         29
#define AO_TMRDACWRs_In_Progress_St             _bit5

#define AO_Mode_1_Register              38
#define AO_UPDATE_Source_Select(x)              (((x)&0x1f)<<11)
#define AO_UI_Source_Select(x)                  (((x)&0x1f)<<6)
#define AO_Multiple_Channels                    _bit5
#define AO_UPDATE_Source_Polarity               _bit4
#define AO_UI_Source_Polarity                   _bit3
#define AO_UC_Switch_Load_Every_TC              _bit2
#define AO_Continuous                           _bit1
#define AO_Trigger_Once                         _bit0

#define AO_Mode_2_Register              39
#define AO_FIFO_Mode_Mask                       ( 0x3 << 14 )
#define AO_FIFO_Mode_HF_to_F                    (3<<14)
#define AO_FIFO_Mode_F                          (2<<14)
#define AO_FIFO_Mode_HF                         (1<<14)
#define AO_FIFO_Mode_E                          (0<<14)
#define AO_FIFO_Retransmit_Enable               _bit13
#define AO_START1_Disable                       _bit12
#define AO_UC_Initial_Load_Source               _bit11
#define AO_UC_Write_Switch                      _bit10
#define AO_UI2_Initial_Load_Source              _bit9
#define AO_UI2_Reload_Mode                      _bit8
#define AO_UI_Initial_Load_Source               _bit7
#define AO_UI_Reload_Mode(x)                    (((x) & 0x7) << 4)
#define AO_UI_Write_Switch                      _bit3
#define AO_BC_Initial_Load_Source               _bit2
#define AO_BC_Reload_Mode                       _bit1
#define AO_BC_Write_Switch                      _bit0

#define AO_UI_Load_A_Register           40
#define AO_UI_Load_A_Register_High      40
#define AO_UI_Load_A_Register_Low       41
#define AO_UI_Load_B_Register           42
#define AO_UI_Save_Registers            16
#define AO_BC_Load_A_Register           44
#define AO_BC_Load_A_Register_High      44
#define AO_BC_Load_A_Register_Low       45
#define AO_BC_Load_B_Register           46
#define AO_BC_Load_B_Register_High      46
#define AO_BC_Load_B_Register_Low       47
#define AO_BC_Save_Registers            18
#define AO_UC_Load_A_Register           48
#define AO_UC_Load_A_Register_High      48
#define AO_UC_Load_A_Register_Low       49
#define AO_UC_Load_B_Register           50
#define AO_UC_Save_Registers            20

#define Clock_and_FOUT_Register         56
#define FOUT_Enable                             _bit15
#define FOUT_Timebase_Select                    _bit14
#define DIO_Serial_Out_Divide_By_2              _bit13
#define Slow_Internal_Time_Divide_By_2          _bit12
#define Slow_Internal_Timebase                  _bit11
#define G_Source_Divide_By_2                    _bit10
#define Clock_To_Board_Divide_By_2              _bit9
#define Clock_To_Board                          _bit8
#define AI_Output_Divide_By_2                   _bit7
#define AI_Source_Divide_By_2                   _bit6
#define AO_Output_Divide_By_2                   _bit5
#define AO_Source_Divide_By_2                   _bit4
#define FOUT_Divider_mask                       0xf
#define FOUT_Divider(x)                         (((x) & 0xf) << 0)

#define IO_Bidirection_Pin_Register     57
#define RTSI_Trig_Direction_Register    58
#define Drive_RTSI_Clock_Bit                    0x1
#define Use_RTSI_Clock_Bit                      0x2

static inline unsigned int RTSI_Output_Bit(unsigned channel, int is_mseries)
{
        unsigned max_channel;
        unsigned base_bit_shift;
        if(is_mseries)
        {
                base_bit_shift = 8;
                max_channel = 7;
        }else
        {
                base_bit_shift = 9;
                max_channel = 6;
        }
        if(channel > max_channel)
        {
                rtdm_printk("%s: bug, invalid RTSI_channel=%i\n",
                            __FUNCTION__, channel);
                return 0;
        }
        return 1 << (base_bit_shift + channel);
}

#define Interrupt_Control_Register      59
#define Interrupt_B_Enable                      _bit15
#define Interrupt_B_Output_Select(x)            ((x)<<12)
#define Interrupt_A_Enable                      _bit11
#define Interrupt_A_Output_Select(x)            ((x)<<8)
#define Pass_Thru_0_Interrupt_Polarity          _bit3
#define Pass_Thru_1_Interrupt_Polarity          _bit2
#define Interrupt_Output_On_3_Pins              _bit1
#define Interrupt_Output_Polarity               _bit0

#define AI_Output_Control_Register      60
#define AI_START_Output_Select                  _bit10
#define AI_SCAN_IN_PROG_Output_Select(x)        (((x) & 0x3) << 8)
#define AI_EXTMUX_CLK_Output_Select(x)          (((x) & 0x3) << 6)
#define AI_LOCALMUX_CLK_Output_Select(x)        ((x)<<4)
#define AI_SC_TC_Output_Select(x)               ((x)<<2)
#define AI_CONVERT_Output_High_Z                0
#define AI_CONVERT_Output_Ground                1
#define AI_CONVERT_Output_Enable_Low            2
#define AI_CONVERT_Output_Enable_High           3
#define AI_CONVERT_Output_Select(x)             ((x) & 0x3)

#define AI_START_STOP_Select_Register   62
#define AI_START_Polarity                       _bit15
#define AI_STOP_Polarity                        _bit14
#define AI_STOP_Sync                            _bit13
#define AI_STOP_Edge                            _bit12
#define AI_STOP_Select(a)                       (((a) & 0x1f)<<7)
#define AI_START_Sync                           _bit6
#define AI_START_Edge                           _bit5
#define AI_START_Select(a)                      ((a) & 0x1f)

#define AI_Trigger_Select_Register      63
#define AI_START1_Polarity                      _bit15
#define AI_START2_Polarity                      _bit14
#define AI_START2_Sync                          _bit13
#define AI_START2_Edge                          _bit12
#define AI_START2_Select(a)                     (((a) & 0x1f) << 7)
#define AI_START1_Sync                          _bit6
#define AI_START1_Edge                          _bit5
#define AI_START1_Select(a)                     ((a) & 0x1f)

#define AI_DIV_Load_A_Register  64

#define AO_Start_Select_Register        66
#define AO_UI2_Software_Gate                    _bit15
#define AO_UI2_External_Gate_Polarity           _bit14
#define AO_START_Polarity                       _bit13
#define AO_AOFREQ_Enable                        _bit12
#define AO_UI2_External_Gate_Select(a)          (((a) & 0x1f) << 7)
#define AO_START_Sync                           _bit6
#define AO_START_Edge                           _bit5
#define AO_START_Select(a)                      ((a) & 0x1f)

#define AO_Trigger_Select_Register      67
#define AO_UI2_External_Gate_Enable             _bit15
#define AO_Delayed_START1                       _bit14
#define AO_START1_Polarity                      _bit13
#define AO_UI2_Source_Polarity                  _bit12
#define AO_UI2_Source_Select(x)                 (((x)&0x1f)<<7)
#define AO_START1_Sync                          _bit6
#define AO_START1_Edge                          _bit5
#define AO_START1_Select(x)                     (((x)&0x1f)<<0)

#define AO_Mode_3_Register              70
#define AO_UI2_Switch_Load_Next_TC              _bit13
#define AO_UC_Switch_Load_Every_BC_TC           _bit12
#define AO_Trigger_Length                       _bit11
#define AO_Stop_On_Overrun_Error                _bit5
#define AO_Stop_On_BC_TC_Trigger_Error          _bit4
#define AO_Stop_On_BC_TC_Error                  _bit3
#define AO_Not_An_UPDATE                        _bit2
#define AO_Software_Gate                        _bit1
#define AO_Last_Gate_Disable                    _bit0   /* M Series only */

#define Joint_Reset_Register            72
#define Software_Reset                          _bit11
#define AO_Configuration_End                    _bit9
#define AI_Configuration_End                    _bit8
#define AO_Configuration_Start                  _bit5
#define AI_Configuration_Start                  _bit4
#define G1_Reset                                _bit3
#define G0_Reset                                _bit2
#define AO_Reset                                _bit1
#define AI_Reset                                _bit0

#define Interrupt_A_Enable_Register     73
#define Pass_Thru_0_Interrupt_Enable            _bit9
#define G0_Gate_Interrupt_Enable                _bit8
#define AI_FIFO_Interrupt_Enable                _bit7
#define G0_TC_Interrupt_Enable                  _bit6
#define AI_Error_Interrupt_Enable               _bit5
#define AI_STOP_Interrupt_Enable                _bit4
#define AI_START_Interrupt_Enable               _bit3
#define AI_START2_Interrupt_Enable              _bit2
#define AI_START1_Interrupt_Enable              _bit1
#define AI_SC_TC_Interrupt_Enable               _bit0

#define Interrupt_B_Enable_Register     75
#define Pass_Thru_1_Interrupt_Enable            _bit11
#define G1_Gate_Interrupt_Enable                _bit10
#define G1_TC_Interrupt_Enable                  _bit9
#define AO_FIFO_Interrupt_Enable                _bit8
#define AO_UI2_TC_Interrupt_Enable              _bit7
#define AO_UC_TC_Interrupt_Enable               _bit6
#define AO_Error_Interrupt_Enable               _bit5
#define AO_STOP_Interrupt_Enable                _bit4
#define AO_START_Interrupt_Enable               _bit3
#define AO_UPDATE_Interrupt_Enable              _bit2
#define AO_START1_Interrupt_Enable              _bit1
#define AO_BC_TC_Interrupt_Enable               _bit0

#define Second_IRQ_A_Enable_Register    74
#define AI_SC_TC_Second_Irq_Enable              _bit0
#define AI_START1_Second_Irq_Enable             _bit1
#define AI_START2_Second_Irq_Enable             _bit2
#define AI_START_Second_Irq_Enable              _bit3
#define AI_STOP_Second_Irq_Enable               _bit4
#define AI_Error_Second_Irq_Enable              _bit5
#define G0_TC_Second_Irq_Enable                 _bit6
#define AI_FIFO_Second_Irq_Enable               _bit7
#define G0_Gate_Second_Irq_Enable               _bit8
#define Pass_Thru_0_Second_Irq_Enable           _bit9

#define Second_IRQ_B_Enable_Register    76
#define AO_BC_TC_Second_Irq_Enable              _bit0
#define AO_START1_Second_Irq_Enable             _bit1
#define AO_UPDATE_Second_Irq_Enable             _bit2
#define AO_START_Second_Irq_Enable              _bit3
#define AO_STOP_Second_Irq_Enable               _bit4
#define AO_Error_Second_Irq_Enable              _bit5
#define AO_UC_TC_Second_Irq_Enable              _bit6
#define AO_UI2_TC_Second_Irq_Enable             _bit7
#define AO_FIFO_Second_Irq_Enable               _bit8
#define G1_TC_Second_Irq_Enable                 _bit9
#define G1_Gate_Second_Irq_Enable               _bit10
#define Pass_Thru_1_Second_Irq_Enable           _bit11

#define AI_Personal_Register            77
#define AI_SHIFTIN_Pulse_Width                  _bit15
#define AI_EOC_Polarity                         _bit14
#define AI_SOC_Polarity                         _bit13
#define AI_SHIFTIN_Polarity                     _bit12
#define AI_CONVERT_Pulse_Timebase               _bit11
#define AI_CONVERT_Pulse_Width                  _bit10
#define AI_CONVERT_Original_Pulse               _bit9
#define AI_FIFO_Flags_Polarity                  _bit8
#define AI_Overrun_Mode                         _bit7
#define AI_EXTMUX_CLK_Pulse_Width               _bit6
#define AI_LOCALMUX_CLK_Pulse_Width             _bit5
#define AI_AIFREQ_Polarity                      _bit4

#define AO_Personal_Register            78
#define AO_Interval_Buffer_Mode                 _bit3
#define AO_BC_Source_Select                     _bit4
#define AO_UPDATE_Pulse_Width                   _bit5
#define AO_UPDATE_Pulse_Timebase                _bit6
#define AO_UPDATE_Original_Pulse                _bit7
#define AO_DMA_PIO_Control                      _bit8 /* M Series: reserved */
#define AO_AOFREQ_Polarity                      _bit9 /* M Series: reserved */
#define AO_FIFO_Enable                          _bit10
#define AO_FIFO_Flags_Polarity                  _bit11 /* M Series: reserved */
#define AO_TMRDACWR_Pulse_Width                 _bit12
#define AO_Fast_CPU                             _bit13 /* M Series: reserved */
#define AO_Number_Of_DAC_Packages               _bit14 /* 1 for "single" mode,
                                                          0 for "dual" */
#define AO_Multiple_DACS_Per_Package            _bit15 /* M Series only */

#define RTSI_Trig_A_Output_Register     79

#define RTSI_Trig_B_Output_Register     80
#define RTSI_Sub_Selection_1_Bit                _bit15 /* not for M Series */
#define RTSI_Trig_Output_Bits(x, y)             ((y & 0xf) << ((x % 4) * 4))
#define RTSI_Trig_Output_Mask(x)                (0xf << ((x % 4) * 4))
#define RTSI_Trig_Output_Source(x, y)           ((y >> ((x % 4) * 4)) & 0xf)

#define RTSI_Board_Register             81
#define Write_Strobe_0_Register         82
#define Write_Strobe_1_Register         83
#define Write_Strobe_2_Register         84
#define Write_Strobe_3_Register         85

#define AO_Output_Control_Register      86
#define AO_External_Gate_Enable                 _bit15
#define AO_External_Gate_Select(x)              (((x)&0x1f)<<10)
#define AO_Number_Of_Channels(x)                (((x)&0xf)<<6)
#define AO_UPDATE2_Output_Select(x)             (((x)&0x3)<<4)
#define AO_External_Gate_Polarity               _bit3
#define AO_UPDATE2_Output_Toggle                _bit2
#define AO_Update_Output_High_Z                 0
#define AO_Update_Output_Ground                 1
#define AO_Update_Output_Enable_Low             2
#define AO_Update_Output_Enable_High            3
#define AO_UPDATE_Output_Select(x)              (x&0x3)

#define AI_Mode_3_Register              87
#define AI_Trigger_Length                       _bit15
#define AI_Delay_START                          _bit14
#define AI_Software_Gate                        _bit13
#define AI_SI_Special_Trigger_Delay             _bit12
#define AI_SI2_Source_Select                    _bit11
#define AI_Delayed_START2                       _bit10
#define AI_Delayed_START1                       _bit9
#define AI_External_Gate_Mode                   _bit8
#define AI_FIFO_Mode_HF_to_E                    (3<<6)
#define AI_FIFO_Mode_F                          (2<<6)
#define AI_FIFO_Mode_HF                         (1<<6)
#define AI_FIFO_Mode_NE                         (0<<6)
#define AI_External_Gate_Polarity               _bit5
#define AI_External_Gate_Select(a)              ((a) & 0x1f)

#define G_Autoincrement_Register(a)     (68+(a))
#define G_Command_Register(a)           (6+(a))
#define G_HW_Save_Register(a)           (8+(a)*2)
#define G_HW_Save_Register_High(a)      (8+(a)*2)
#define G_HW_Save_Register_Low(a)       (9+(a)*2)
#define G_Input_Select_Register(a)      (36+(a))
#define G_Load_A_Register(a)            (28+(a)*4)
#define G_Load_A_Register_High(a)       (28+(a)*4)
#define G_Load_A_Register_Low(a)        (29+(a)*4)
#define G_Load_B_Register(a)            (30+(a)*4)
#define G_Load_B_Register_High(a)       (30+(a)*4)
#define G_Load_B_Register_Low(a)        (31+(a)*4)
#define G_Mode_Register(a)              (26+(a))
#define G_Save_Register(a)              (12+(a)*2)
#define G_Save_Register_High(a)         (12+(a)*2)
#define G_Save_Register_Low(a)          (13+(a)*2)
#define G_Status_Register               4
#define Analog_Trigger_Etc_Register     61

/* command register */
#define G_Disarm_Copy                   _bit15          /* strobe */
#define G_Save_Trace_Copy               _bit14
#define G_Arm_Copy                      _bit13          /* strobe */
#define G_Bank_Switch_Start             _bit10          /* strobe */
#define G_Little_Big_Endian             _bit9
#define G_Synchronized_Gate             _bit8
#define G_Write_Switch                  _bit7
#define G_Up_Down(a)                    (((a)&0x03)<<5)
#define G_Disarm                        _bit4           /* strobe */
#define G_Analog_Trigger_Reset          _bit3           /* strobe */
#define G_Save_Trace                    _bit1
#define G_Arm                           _bit0           /* strobe */

/* channel agnostic names for the command register #defines */
#define G_Bank_Switch_Enable            _bit12
#define G_Bank_Switch_Mode              _bit11
#define G_Load                          _bit2           /* strobe */

/* input select register */
#define G_Gate_Select(a)                (((a)&0x1f)<<7)
#define G_Source_Select(a)              (((a)&0x1f)<<2)
#define G_Write_Acknowledges_Irq        _bit1
#define G_Read_Acknowledges_Irq         _bit0

/* same input select register, but with channel agnostic names */
#define G_Source_Polarity               _bit15
#define G_Output_Polarity               _bit14
#define G_OR_Gate                       _bit13
#define G_Gate_Select_Load_Source       _bit12

/* mode register */
#define G_Loading_On_TC                 _bit12
#define G_Output_Mode(a)                (((a)&0x03)<<8)
#define G_Trigger_Mode_For_Edge_Gate(a) (((a)&0x03)<<3)
#define G_Gating_Mode(a)                (((a)&0x03)<<0)

/* same input mode register, but with channel agnostic names */
#define G_Load_Source_Select            _bit7
#define G_Reload_Source_Switching       _bit15
#define G_Loading_On_Gate               _bit14
#define G_Gate_Polarity                 _bit13

#define G_Counting_Once(a)              (((a)&0x03)<<10)
#define G_Stop_Mode(a)                  (((a)&0x03)<<5)
#define G_Gate_On_Both_Edges            _bit2

/* G_Status_Register */
#define G1_Gate_Error_St                _bit15
#define G0_Gate_Error_St                _bit14
#define G1_TC_Error_St                  _bit13
#define G0_TC_Error_St                  _bit12
#define G1_No_Load_Between_Gates_St     _bit11
#define G0_No_Load_Between_Gates_St     _bit10
#define G1_Armed_St                     _bit9
#define G0_Armed_St                     _bit8
#define G1_Stale_Data_St                _bit7
#define G0_Stale_Data_St                _bit6
#define G1_Next_Load_Source_St          _bit5
#define G0_Next_Load_Source_St          _bit4
#define G1_Counting_St                  _bit3
#define G0_Counting_St                  _bit2
#define G1_Save_St                      _bit1
#define G0_Save_St                      _bit0

/* general purpose counter timer */
#define G_Autoincrement(a)              ((a)<<0)

/*Analog_Trigger_Etc_Register*/
#define Analog_Trigger_Mode(x) ((x) & 0x7)
#define Analog_Trigger_Enable _bit3
#define Analog_Trigger_Drive _bit4
#define GPFO_1_Output_Select            _bit7
#define GPFO_0_Output_Select(a)         ((a)<<11)
#define GPFO_0_Output_Enable            _bit14
#define GPFO_1_Output_Enable            _bit15

/* Additional windowed registers unique to E series */

/* 16 bit registers shadowed from DAQ-STC */
#define Window_Address                  0x00
#define Window_Data                     0x02

#define Configuration_Memory_Clear      82
#define ADC_FIFO_Clear                  83
#define DAC_FIFO_Clear                  84

/* i/o port offsets */

/* 8 bit registers */
#define XXX_Status                      0x01
#define PROMOUT                                 _bit0
#define AI_FIFO_LOWER_NOT_EMPTY                 _bit3

#define Serial_Command                  0x0d
#define Misc_Command                    0x0f
#define Port_A                          0x19
#define Port_B                          0x1b
#define Port_C                          0x1d
#define Configuration                   0x1f
#define Strobes                         0x01
#define Channel_A_Mode                  0x03
#define Channel_B_Mode                  0x05
#define Channel_C_Mode                  0x07
#define AI_AO_Select                    0x09
#define AI_DMA_Select_Shift             0
#define AI_DMA_Select_Mask              0xf
#define AO_DMA_Select_Shift             4
#define AO_DMA_Select_Mask              (0xf << AO_DMA_Select_Shift)

#define G0_G1_Select                    0x0b

static inline unsigned ni_stc_dma_channel_select_bitfield(unsigned channel)
{
        if(channel < 4) return 1 << channel;
        if(channel == 4) return 0x3;
        if(channel == 5) return 0x5;
        BUG();
        return 0;
}
static inline unsigned GPCT_DMA_Select_Bits(unsigned gpct_index, unsigned mite_channel)
{
        BUG_ON(gpct_index > 1);
        return ni_stc_dma_channel_select_bitfield(mite_channel) << (4 * gpct_index);
}
static inline unsigned GPCT_DMA_Select_Mask(unsigned gpct_index)
{
        BUG_ON(gpct_index > 1);
        return 0xf << (4 * gpct_index);
}

/* 16 bit registers */

#define Configuration_Memory_Low        0x10
#define AI_DITHER                               _bit9
#define AI_LAST_CHANNEL                         _bit15

#define Configuration_Memory_High       0x12
#define AI_AC_COUPLE                            _bit11
#define AI_DIFFERENTIAL                         _bit12
#define AI_COMMON                               _bit13
#define AI_GROUND                               (_bit12|_bit13)
#define AI_CONFIG_CHANNEL(x)                    (x&0x3f)

#define ADC_FIFO_Data_Register          0x1c

#define AO_Configuration                0x16
#define AO_Bipolar              _bit0
#define AO_Deglitch             _bit1
#define AO_Ext_Ref              _bit2
#define AO_Ground_Ref           _bit3
#define AO_Channel(x)           ((x) << 8)

#define DAC_FIFO_Data                   0x1e
#define DAC0_Direct_Data                0x18
#define DAC1_Direct_Data                0x1a

/* 611x registers (these boards differ from the e-series) */

#define Magic_611x                      0x19 /* w8 (new) */
#define Calibration_Channel_Select_611x 0x1a /* w16 (new) */
#define ADC_FIFO_Data_611x              0x1c /* r32 (incompatible) */
#define AI_FIFO_Offset_Load_611x        0x05 /* r8 (new) */
#define DAC_FIFO_Data_611x              0x14 /* w32 (incompatible) */
#define Cal_Gain_Select_611x            0x05 /* w8 (new) */

#define AO_Window_Address_611x          0x18
#define AO_Window_Data_611x             0x1e

/* 6143 registers */
#define Magic_6143                      0x19 /* w8 */
#define G0G1_DMA_Select_6143            0x0B /* w8 */
#define PipelineDelay_6143              0x1f /* w8 */
#define EOC_Set_6143                    0x1D /* w8 */
#define AIDMA_Select_6143               0x09 /* w8 */
#define AIFIFO_Data_6143                0x8C /* w32 */
#define AIFIFO_Flag_6143                0x84 /* w32 */
#define AIFIFO_Control_6143             0x88 /* w32 */
#define AIFIFO_Status_6143              0x88 /* w32 */
#define AIFIFO_DMAThreshold_6143        0x90 /* w32 */
#define AIFIFO_Words_Available_6143     0x94 /* w32 */

#define Calibration_Channel_6143        0x42 /* w16 */
#define Calibration_LowTime_6143        0x20 /* w16 */
#define Calibration_HighTime_6143       0x22 /* w16 */
#define Relay_Counter_Load_Val__6143    0x4C /* w32 */
#define Signature_6143                  0x50 /* w32 */
#define Release_Date_6143               0x54 /* w32 */
#define Release_Oldest_Date_6143        0x58 /* w32 */

#define Calibration_Channel_6143_RelayOn        0x8000  /* Calibration relay switch On */
#define Calibration_Channel_6143_RelayOff       0x4000  /* Calibration relay switch Off */
#define Calibration_Channel_Gnd_Gnd     0x00    /* Offset Calibration */
#define Calibration_Channel_2v5_Gnd     0x02    /* 2.5V Reference */
#define Calibration_Channel_Pwm_Gnd     0x05    /* +/- 5V Self Cal */
#define Calibration_Channel_2v5_Pwm     0x0a    /* PWM Calibration */
#define Calibration_Channel_Pwm_Pwm     0x0d    /* CMRR */
#define Calibration_Channel_Gnd_Pwm     0x0e    /* PWM Calibration */

/* 671x, 611x registers */

/* 671xi 611x windowed ao registers */
#define AO_Immediate_671x                       0x11 /* W 16 */
#define AO_Timed_611x                           0x10 /* W 16 */
#define AO_FIFO_Offset_Load_611x                0x13 /* W32 */
#define AO_Later_Single_Point_Updates           0x14 /* W 16 */
#define AO_Waveform_Generation_611x             0x15 /* W 16 */
#define AO_Misc_611x                            0x16 /* W 16 */
#define AO_Calibration_Channel_Select_67xx      0x17 /* W 16 */
#define AO_Configuration_2_67xx                 0x18 /* W 16 */
#define CAL_ADC_Command_67xx                    0x19 /* W 8 */
#define CAL_ADC_Status_67xx                     0x1a /* R 8 */
#define CAL_ADC_Data_67xx                       0x1b /* R 16 */
#define CAL_ADC_Config_Data_High_Word_67xx      0x1c /* RW 16 */
#define CAL_ADC_Config_Data_Low_Word_67xx       0x1d /* RW 16 */

static inline unsigned int DACx_Direct_Data_671x(int channel)
{
        return channel;
}

#define CLEAR_WG                                _bit0

#define CSCFG_CAL_CONTROL_MASK                  0x7
#define CSCFG_SELF_CAL_OFFSET                   0x1
#define CSCFG_SELF_CAL_GAIN                     0x2
#define CSCFG_SELF_CAL_OFFSET_GAIN              0x3
#define CSCFG_SYSTEM_CAL_OFFSET                 0x5
#define CSCFG_SYSTEM_CAL_GAIN                   0x6
#define CSCFG_DONE                              (1 << 3)
#define CSCFG_POWER_SAVE_SELECT                 (1 << 4)
#define CSCFG_PORT_MODE                         (1 << 5)
#define CSCFG_RESET_VALID                       (1 << 6)
#define CSCFG_RESET                             (1 << 7)
#define CSCFG_UNIPOLAR                          (1 << 12)
#define CSCFG_WORD_RATE_2180_CYCLES             (0x0 << 13)
#define CSCFG_WORD_RATE_1092_CYCLES             (0x1 << 13)
#define CSCFG_WORD_RATE_532_CYCLES              (0x2 << 13)
#define CSCFG_WORD_RATE_388_CYCLES              (0x3 << 13)
#define CSCFG_WORD_RATE_324_CYCLES              (0x4 << 13)
#define CSCFG_WORD_RATE_17444_CYCLES            (0x5 << 13)
#define CSCFG_WORD_RATE_8724_CYCLES             (0x6 << 13)
#define CSCFG_WORD_RATE_4364_CYCLES             (0x7 << 13)
#define CSCFG_WORD_RATE_MASK                    (0x7 << 13)
#define CSCFG_LOW_POWER                         (1 << 16)

#define CS5529_CONFIG_DOUT(x)                   (1 << (18 + x))
#define CS5529_CONFIG_AOUT(x)                   (1 << (22 + x))

/* cs5529 command bits */
#define CSCMD_POWER_SAVE                        _bit0
#define CSCMD_REGISTER_SELECT_MASK              0xe
#define CSCMD_OFFSET_REGISTER                   0x0
#define CSCMD_GAIN_REGISTER                     _bit1
#define CSCMD_CONFIG_REGISTER                   _bit2
#define CSCMD_READ                              _bit4
#define CSCMD_CONTINUOUS_CONVERSIONS            _bit5
#define CSCMD_SINGLE_CONVERSION                 _bit6
#define CSCMD_COMMAND                           _bit7

/* cs5529 status bits */
#define CSS_ADC_BUSY                            _bit0
#define CSS_OSC_DETECT                          _bit1 /* indicates adc error */
#define CSS_OVERRANGE                           _bit3

#define SerDacLd(x)                     (0x08<<(x))

/*
        This is stuff unique to the NI E series drivers,
        but I thought I'd put it here anyway.
*/

enum
{
        ai_gain_16 = 0,
        ai_gain_8,
        ai_gain_14,
        ai_gain_4,
        ai_gain_611x,
        ai_gain_622x,
        ai_gain_628x,
        ai_gain_6143
};
enum caldac_enum
{
        caldac_none=0,
        mb88341,
        dac8800,
        dac8043,
        ad8522,
        ad8804,
        ad8842,
        ad8804_debug
};
enum ni_reg_type
{
        ni_reg_normal = 0x0,
        ni_reg_611x = 0x1,
        ni_reg_6711 = 0x2,
        ni_reg_6713 = 0x4,
        ni_reg_67xx_mask = 0x6,
        ni_reg_6xxx_mask = 0x7,
        ni_reg_622x = 0x8,
        ni_reg_625x = 0x10,
        ni_reg_628x = 0x18,
        ni_reg_m_series_mask = 0x18,
        ni_reg_6143 = 0x20
};

/* M Series registers offsets */
#define M_Offset_CDIO_DMA_Select                0x7 /* write */
#define M_Offset_SCXI_Status                    0x7 /* read */
#define M_Offset_AI_AO_Select                   0x9 /* write, same offset as e-series */
#define M_Offset_SCXI_Serial_Data_In            0x9 /* read */
#define M_Offset_G0_G1_Select                   0xb /* write, same offset as e-series */
#define M_Offset_Misc_Command                   0xf
#define M_Offset_SCXI_Serial_Data_Out           0x11
#define M_Offset_SCXI_Control                   0x13
#define M_Offset_SCXI_Output_Enable             0x15
#define M_Offset_AI_FIFO_Data                   0x1c
#define M_Offset_Static_Digital_Output          0x24 /* write */
#define M_Offset_Static_Digital_Input           0x24 /* read */
#define M_Offset_DIO_Direction                  0x28
#define M_Offset_Cal_PWM                        0x40
#define M_Offset_AI_Config_FIFO_Data            0x5e
#define M_Offset_Interrupt_C_Enable             0x88 /* write */
#define M_Offset_Interrupt_C_Status             0x88 /* read */
#define M_Offset_Analog_Trigger_Control         0x8c
#define M_Offset_AO_Serial_Interrupt_Enable     0xa0
#define M_Offset_AO_Serial_Interrupt_Ack        0xa1 /* write */
#define M_Offset_AO_Serial_Interrupt_Status     0xa1 /* read */
#define M_Offset_AO_Calibration                 0xa3
#define M_Offset_AO_FIFO_Data                   0xa4
#define M_Offset_PFI_Filter                     0xb0
#define M_Offset_RTSI_Filter                    0xb4
#define M_Offset_SCXI_Legacy_Compatibility      0xbc
#define M_Offset_Interrupt_A_Ack                0x104 /* write */
#define M_Offset_AI_Status_1                    0x104 /* read */
#define M_Offset_Interrupt_B_Ack                0x106 /* write */
#define M_Offset_AO_Status_1                    0x106 /* read */
#define M_Offset_AI_Command_2                   0x108 /* write */
#define M_Offset_G01_Status                     0x108 /* read */
#define M_Offset_AO_Command_2                   0x10a
#define M_Offset_AO_Status_2                    0x10c /* read */
#define M_Offset_G0_Command                     0x10c /* write */
#define M_Offset_G1_Command                     0x10e /* write */
#define M_Offset_G0_HW_Save                     0x110
#define M_Offset_G0_HW_Save_High                0x110
#define M_Offset_AI_Command_1                   0x110
#define M_Offset_G0_HW_Save_Low                 0x112
#define M_Offset_AO_Command_1                   0x112
#define M_Offset_G1_HW_Save                     0x114
#define M_Offset_G1_HW_Save_High                0x114
#define M_Offset_G1_HW_Save_Low                 0x116
#define M_Offset_AI_Mode_1                      0x118
#define M_Offset_G0_Save                        0x118
#define M_Offset_G0_Save_High                   0x118
#define M_Offset_AI_Mode_2                      0x11a
#define M_Offset_G0_Save_Low                    0x11a
#define M_Offset_AI_SI_Load_A                   0x11c
#define M_Offset_G1_Save                        0x11c
#define M_Offset_G1_Save_High                   0x11c
#define M_Offset_G1_Save_Low                    0x11e
#define M_Offset_AI_SI_Load_B                   0x120 /* write */
#define M_Offset_AO_UI_Save                     0x120 /* read */
#define M_Offset_AI_SC_Load_A                   0x124 /* write */
#define M_Offset_AO_BC_Save                     0x124 /* read */
#define M_Offset_AI_SC_Load_B                   0x128 /* write */
#define M_Offset_AO_UC_Save                     0x128 /* read */
#define M_Offset_AI_SI2_Load_A                  0x12c
#define M_Offset_AI_SI2_Load_B                  0x130
#define M_Offset_G0_Mode                        0x134
#define M_Offset_G1_Mode                        0x136 /* write */
#define M_Offset_Joint_Status_1                 0x136 /* read */
#define M_Offset_G0_Load_A                      0x138
#define M_Offset_Joint_Status_2                 0x13a
#define M_Offset_G0_Load_B                      0x13c
#define M_Offset_G1_Load_A                      0x140
#define M_Offset_G1_Load_B                      0x144
#define M_Offset_G0_Input_Select                0x148
#define M_Offset_G1_Input_Select                0x14a
#define M_Offset_AO_Mode_1                      0x14c
#define M_Offset_AO_Mode_2                      0x14e
#define M_Offset_AO_UI_Load_A                   0x150
#define M_Offset_AO_UI_Load_B                   0x154
#define M_Offset_AO_BC_Load_A                   0x158
#define M_Offset_AO_BC_Load_B                   0x15c
#define M_Offset_AO_UC_Load_A                   0x160
#define M_Offset_AO_UC_Load_B                   0x164
#define M_Offset_Clock_and_FOUT                 0x170
#define M_Offset_IO_Bidirection_Pin             0x172
#define M_Offset_RTSI_Trig_Direction            0x174
#define M_Offset_Interrupt_Control              0x176
#define M_Offset_AI_Output_Control              0x178
#define M_Offset_Analog_Trigger_Etc             0x17a
#define M_Offset_AI_START_STOP_Select           0x17c
#define M_Offset_AI_Trigger_Select              0x17e
#define M_Offset_AI_SI_Save                     0x180 /* read */
#define M_Offset_AI_DIV_Load_A                  0x180 /* write */
#define M_Offset_AI_SC_Save                     0x184 /* read */
#define M_Offset_AO_Start_Select                0x184 /* write */
#define M_Offset_AO_Trigger_Select              0x186
#define M_Offset_AO_Mode_3                      0x18c
#define M_Offset_G0_Autoincrement               0x188
#define M_Offset_G1_Autoincrement               0x18a
#define M_Offset_Joint_Reset                    0x190
#define M_Offset_Interrupt_A_Enable             0x192
#define M_Offset_Interrupt_B_Enable             0x196
#define M_Offset_AI_Personal                    0x19a
#define M_Offset_AO_Personal                    0x19c
#define M_Offset_RTSI_Trig_A_Output             0x19e
#define M_Offset_RTSI_Trig_B_Output             0x1a0
#define M_Offset_RTSI_Shared_MUX                0x1a2
#define M_Offset_AO_Output_Control              0x1ac
#define M_Offset_AI_Mode_3                      0x1ae
#define M_Offset_Configuration_Memory_Clear     0x1a4
#define M_Offset_AI_FIFO_Clear                  0x1a6
#define M_Offset_AO_FIFO_Clear                  0x1a8
#define M_Offset_G0_Counting_Mode               0x1b0
#define M_Offset_G1_Counting_Mode               0x1b2
#define M_Offset_G0_Second_Gate                 0x1b4
#define M_Offset_G1_Second_Gate                 0x1b6
#define M_Offset_G0_DMA_Config                  0x1b8 /* write */
#define M_Offset_G0_DMA_Status                  0x1b8 /* read */
#define M_Offset_G1_DMA_Config                  0x1ba /* write */
#define M_Offset_G1_DMA_Status                  0x1ba /* read */
#define M_Offset_G0_MSeries_ABZ                 0x1c0
#define M_Offset_G1_MSeries_ABZ                 0x1c2
#define M_Offset_Clock_and_Fout2                0x1c4
#define M_Offset_PLL_Control                    0x1c6
#define M_Offset_PLL_Status                     0x1c8
#define M_Offset_PFI_Output_Select_1            0x1d0
#define M_Offset_PFI_Output_Select_2            0x1d2
#define M_Offset_PFI_Output_Select_3            0x1d4
#define M_Offset_PFI_Output_Select_4            0x1d6
#define M_Offset_PFI_Output_Select_5            0x1d8
#define M_Offset_PFI_Output_Select_6            0x1da
#define M_Offset_PFI_DI                         0x1dc
#define M_Offset_PFI_DO                         0x1de
#define M_Offset_AI_Config_FIFO_Bypass          0x218
#define M_Offset_SCXI_DIO_Enable                0x21c
#define M_Offset_CDI_FIFO_Data                  0x220 /* read */
#define M_Offset_CDO_FIFO_Data                  0x220 /* write */
#define M_Offset_CDIO_Status                    0x224 /* read */
#define M_Offset_CDIO_Command                   0x224 /* write */
#define M_Offset_CDI_Mode                       0x228
#define M_Offset_CDO_Mode                       0x22c
#define M_Offset_CDI_Mask_Enable                0x230
#define M_Offset_CDO_Mask_Enable                0x234
#define M_Offset_AO_Waveform_Order(x)           (0xc2 + 0x4 * x)
#define M_Offset_AO_Config_Bank(x)              (0xc3 + 0x4 * x)
#define M_Offset_DAC_Direct_Data(x)             (0xc0 + 0x4 * x)
#define M_Offset_Gen_PWM(x)                     (0x44 + 0x2 * x)

static inline int M_Offset_Static_AI_Control(int i)
{
        int offset[] =
        {
                0x64,
                0x261,
                0x262,
                0x263,
        };
        if(((unsigned)i) >= sizeof(offset) / sizeof(offset[0]))
        {
                rtdm_printk("%s: invalid channel=%i\n", __FUNCTION__, i);
                return offset[0];
        }
        return offset[i];
};
static inline int M_Offset_AO_Reference_Attenuation(int channel)
{
        int offset[] =
        {
                0x264,
                0x265,
                0x266,
                0x267
        };
        if(((unsigned)channel) >= sizeof(offset) / sizeof(offset[0]))
        {
                rtdm_printk("%s: invalid channel=%i\n", __FUNCTION__, channel);
                return offset[0];
        }
        return offset[channel];
};
static inline unsigned M_Offset_PFI_Output_Select(unsigned n)
{
        if(n < 1 || n > NUM_PFI_OUTPUT_SELECT_REGS)
        {
                rtdm_printk("%s: invalid pfi output select register=%i\n", __FUNCTION__, n);
                return M_Offset_PFI_Output_Select_1;
        }
        return M_Offset_PFI_Output_Select_1 + (n - 1) * 2;
}

#define MSeries_AI_Config_Channel_Type_Mask                     (0x7 << 6)
#define MSeries_AI_Config_Channel_Type_Calibration_Bits         0x0
#define MSeries_AI_Config_Channel_Type_Differential_Bits        (0x1 << 6)
#define MSeries_AI_Config_Channel_Type_Common_Ref_Bits          (0x2 << 6)
#define MSeries_AI_Config_Channel_Type_Ground_Ref_Bits          (0x3 << 6)
#define MSeries_AI_Config_Channel_Type_Aux_Bits                 (0x5 << 6)
#define MSeries_AI_Config_Channel_Type_Ghost_Bits               (0x7 << 6)
#define MSeries_AI_Config_Polarity_Bit                          0x1000 /* 0 for 2's complement encoding */
#define MSeries_AI_Config_Dither_Bit                            0x2000
#define MSeries_AI_Config_Last_Channel_Bit                      0x4000
#define MSeries_AI_Config_Channel_Bits(x)                       (x & 0xf)
#define MSeries_AI_Config_Gain_Bits(x)                          ((x & 0x7) << 9)

static inline
unsigned int MSeries_AI_Config_Bank_Bits(unsigned int reg_type,
                                         unsigned int channel)
{
        unsigned int bits = channel & 0x30;
        if (reg_type == ni_reg_622x) {
                if (channel & 0x40)
                        bits |= 0x400;
        }
        return bits;
}

#define MSeries_PLL_In_Source_Select_RTSI0_Bits                 0xb
#define MSeries_PLL_In_Source_Select_Star_Trigger_Bits          0x14
#define MSeries_PLL_In_Source_Select_RTSI7_Bits                 0x1b
#define MSeries_PLL_In_Source_Select_PXI_Clock10                0x1d
#define MSeries_PLL_In_Source_Select_Mask                       0x1f
#define MSeries_Timebase1_Select_Bit                            0x20 /* use PLL for timebase 1 */
#define MSeries_Timebase3_Select_Bit                            0x40 /* use PLL for timebase 3 */
/* Use 10MHz instead of 20MHz for RTSI clock frequency.  Appears
   to have no effect, at least on pxi-6281, which always uses
   20MHz rtsi clock frequency */
#define MSeries_RTSI_10MHz_Bit                                  0x80

static inline
unsigned int MSeries_PLL_In_Source_Select_RTSI_Bits(unsigned int RTSI_channel)
{
        if(RTSI_channel > 7)
        {
                rtdm_printk("%s: bug, invalid RTSI_channel=%i\n", __FUNCTION__, RTSI_channel);
                return 0;
        }
        if(RTSI_channel == 7) return MSeries_PLL_In_Source_Select_RTSI7_Bits;
        else return MSeries_PLL_In_Source_Select_RTSI0_Bits + RTSI_channel;
}

#define MSeries_PLL_Enable_Bit                                  0x1000
#define MSeries_PLL_VCO_Mode_200_325MHz_Bits                    0x0
#define MSeries_PLL_VCO_Mode_175_225MHz_Bits                    0x2000
#define MSeries_PLL_VCO_Mode_100_225MHz_Bits                    0x4000
#define MSeries_PLL_VCO_Mode_75_150MHz_Bits                     0x6000

static inline
unsigned int MSeries_PLL_Divisor_Bits(unsigned int divisor)
{
        static const unsigned int max_divisor = 0x10;
        if(divisor < 1 || divisor > max_divisor)
        {
                rtdm_printk("%s: bug, invalid divisor=%i\n", __FUNCTION__, divisor);
                return 0;
        }
        return (divisor & 0xf) << 8;
}
static inline
unsigned int MSeries_PLL_Multiplier_Bits(unsigned int multiplier)
{
        static const unsigned int max_multiplier = 0x100;
        if(multiplier < 1 || multiplier > max_multiplier)
        {
                rtdm_printk("%s: bug, invalid multiplier=%i\n", __FUNCTION__, multiplier);
                return 0;
        }
        return multiplier & 0xff;
}

#define MSeries_PLL_Locked_Bit                          0x1

#define MSeries_AI_Bypass_Channel_Mask                  0x7
#define MSeries_AI_Bypass_Bank_Mask                     0x78
#define MSeries_AI_Bypass_Cal_Sel_Pos_Mask              0x380
#define MSeries_AI_Bypass_Cal_Sel_Neg_Mask              0x1c00
#define MSeries_AI_Bypass_Mode_Mux_Mask                 0x6000
#define MSeries_AO_Bypass_AO_Cal_Sel_Mask               0x38000
#define MSeries_AI_Bypass_Gain_Mask                     0x1c0000
#define MSeries_AI_Bypass_Dither_Bit                    0x200000
#define MSeries_AI_Bypass_Polarity_Bit                  0x400000 /* 0 for 2's complement encoding */
#define MSeries_AI_Bypass_Config_FIFO_Bit               0x80000000
#define MSeries_AI_Bypass_Cal_Sel_Pos_Bits(x)           ((x << 7) & \
                                                         MSeries_AI_Bypass_Cal_Sel_Pos_Mask)
#define MSeries_AI_Bypass_Cal_Sel_Neg_Bits(x)           ((x << 10) & \
                                                         MSeries_AI_Bypass_Cal_Sel_Pos_Mask)
#define MSeries_AI_Bypass_Gain_Bits(x)                  ((x << 18) & \
                                                         MSeries_AI_Bypass_Gain_Mask)

#define MSeries_AO_DAC_Offset_Select_Mask               0x7
#define MSeries_AO_DAC_Offset_0V_Bits                   0x0
#define MSeries_AO_DAC_Offset_5V_Bits                   0x1
#define MSeries_AO_DAC_Reference_Mask                   0x38
#define MSeries_AO_DAC_Reference_10V_Internal_Bits      0x0
#define MSeries_AO_DAC_Reference_5V_Internal_Bits       0x8
#define MSeries_AO_Update_Timed_Bit                     0x40
#define MSeries_AO_Bipolar_Bit                          0x80 /* turns on 2's complement encoding */

#define MSeries_Attenuate_x5_Bit                        0x1

#define MSeries_Cal_PWM_High_Time_Bits(x)               ((x << 16) & 0xffff0000)
#define MSeries_Cal_PWM_Low_Time_Bits(x)                (x & 0xffff)

#define MSeries_PFI_Output_Select_Mask(x)               (0x1f << (x % 3) * 5)
#define MSeries_PFI_Output_Select_Bits(x, y)            ((y & 0x1f) << ((x % 3) * 5))
// inverse to MSeries_PFI_Output_Select_Bits
#define MSeries_PFI_Output_Select_Source(x, y)          ((y >> ((x % 3) * 5)) & 0x1f)

#define Gi_DMA_BankSW_Error_Bit                         0x10
#define Gi_DMA_Reset_Bit                                0x8
#define Gi_DMA_Int_Enable_Bit                           0x4
#define Gi_DMA_Write_Bit                                0x2
#define Gi_DMA_Enable_Bit                               0x1

#define MSeries_PFI_Filter_Select_Mask(x)               (0x3 << (x * 2))
#define MSeries_PFI_Filter_Select_Bits(x, y)            ((y << (x * 2)) & \
                                                         MSeries_PFI_Filter_Select_Mask(x))

/* CDIO DMA select bits */
#define CDI_DMA_Select_Shift    0
#define CDI_DMA_Select_Mask     0xf
#define CDO_DMA_Select_Shift    4
#define CDO_DMA_Select_Mask     0xf << CDO_DMA_Select_Shift

/* CDIO status bits */
#define CDO_FIFO_Empty_Bit      0x1
#define CDO_FIFO_Full_Bit       0x2
#define CDO_FIFO_Request_Bit    0x4
#define CDO_Overrun_Bit         0x8
#define CDO_Underflow_Bit       0x10
#define CDI_FIFO_Empty_Bit      0x10000
#define CDI_FIFO_Full_Bit       0x20000
#define CDI_FIFO_Request_Bit    0x40000
#define CDI_Overrun_Bit         0x80000
#define CDI_Overflow_Bit        0x100000

/* CDIO command bits */
#define CDO_Disarm_Bit                                  0x1
#define CDO_Arm_Bit                                     0x2
#define CDI_Disarm_Bit                                  0x4
#define CDI_Arm_Bit                                     0x8
#define CDO_Reset_Bit                                   0x10
#define CDI_Reset_Bit                                   0x20
#define CDO_Error_Interrupt_Enable_Set_Bit              0x40
#define CDO_Error_Interrupt_Enable_Clear_Bit            0x80
#define CDI_Error_Interrupt_Enable_Set_Bit              0x100
#define CDI_Error_Interrupt_Enable_Clear_Bit            0x200
#define CDO_FIFO_Request_Interrupt_Enable_Set_Bit       0x400
#define CDO_FIFO_Request_Interrupt_Enable_Clear_Bit     0x800
#define CDI_FIFO_Request_Interrupt_Enable_Set_Bit       0x1000
#define CDI_FIFO_Request_Interrupt_Enable_Clear_Bit     0x2000
#define CDO_Error_Interrupt_Confirm_Bit                 0x4000
#define CDI_Error_Interrupt_Confirm_Bit                 0x8000
#define CDO_Empty_FIFO_Interrupt_Enable_Set_Bit         0x10000
#define CDO_Empty_FIFO_Interrupt_Enable_Clear_Bit       0x20000
#define CDO_SW_Update_Bit                               0x80000
#define CDI_SW_Update_Bit                               0x100000

/* CDIO mode bits */
#define CDI_Sample_Source_Select_Mask   0x3f
#define CDI_Halt_On_Error_Bit           0x200
/* sample clock on falling edge */
#define CDI_Polarity_Bit                0x400
/* set for half full mode, clear for not empty mode */
#define CDI_FIFO_Mode_Bit               0x800
/* data lanes specify which dio channels map to byte or word accesses
   to the dio fifos */
#define CDI_Data_Lane_Mask              0x3000
#define CDI_Data_Lane_0_15_Bits         0x0
#define CDI_Data_Lane_16_31_Bits        0x1000
#define CDI_Data_Lane_0_7_Bits          0x0
#define CDI_Data_Lane_8_15_Bits         0x1000
#define CDI_Data_Lane_16_23_Bits        0x2000
#define CDI_Data_Lane_24_31_Bits        0x3000

/* CDO mode bits */
#define CDO_Sample_Source_Select_Mask   0x3f
#define CDO_Retransmit_Bit              0x100
#define CDO_Halt_On_Error_Bit           0x200
/* sample clock on falling edge */
#define CDO_Polarity_Bit                0x400
/* set for half full mode, clear for not full mode */
#define CDO_FIFO_Mode_Bit               0x800
/* data lanes specify which dio channels map to byte or word accesses
   to the dio fifos */
#define CDO_Data_Lane_Mask              0x3000
#define CDO_Data_Lane_0_15_Bits         0x0
#define CDO_Data_Lane_16_31_Bits        0x1000
#define CDO_Data_Lane_0_7_Bits          0x0
#define CDO_Data_Lane_8_15_Bits         0x1000
#define CDO_Data_Lane_16_23_Bits        0x2000
#define CDO_Data_Lane_24_31_Bits        0x3000

/* Interrupt C bits */
#define Interrupt_Group_C_Enable_Bit    0x1
#define Interrupt_Group_C_Status_Bit    0x1

#define M_SERIES_EEPROM_SIZE 1024

typedef struct ni_board_struct{
        unsigned short device_id;
        int isapnp_id;
        char *name;

        int n_adchan;
        int adbits;

        int ai_fifo_depth;
        unsigned int alwaysdither : 1;
        int gainlkup;
        int ai_speed;

        int n_aochan;
        int aobits;
        a4l_rngdesc_t *ao_range_table;
        int ao_fifo_depth;

        unsigned ao_speed;

        unsigned num_p0_dio_channels;

        int reg_type;
        unsigned int ao_unipolar : 1;
        unsigned int has_8255 : 1;
        unsigned int has_analog_trig : 1;

        enum caldac_enum caldac[3];
} ni_board;

#define n_ni_boards  (sizeof(ni_boards)/sizeof(ni_board))

#define MAX_N_CALDACS 34
#define MAX_N_AO_CHAN 8
#define NUM_GPCT 2

#define NI_PRIVATE_COMMON                                       \
        uint16_t (*stc_readw)(a4l_dev_t *dev, int register);    \
        uint32_t (*stc_readl)(a4l_dev_t *dev, int register);    \
        void (*stc_writew)(a4l_dev_t *dev, uint16_t value, int register);       \
        void (*stc_writel)(a4l_dev_t *dev, uint32_t value, int register);       \
        \
        int dio_state;                                          \
        int pfi_state;                                          \
        int io_bits;                                            \
        unsigned short dio_output;                              \
        unsigned short dio_control;                             \
        int ao0p,ao1p;                                          \
        int lastchan;                                           \
        int last_do;                                            \
        int rt_irq;                                             \
        int irq_polarity;                                       \
        int irq_pin;                                            \
        int aimode;                                             \
        int ai_continuous;                                      \
        int blocksize;                                          \
        int n_left;                                             \
        unsigned int ai_calib_source;                           \
        unsigned int ai_calib_source_enabled;                   \
        a4l_lock_t window_lock; \
        a4l_lock_t soft_reg_copy_lock; \
        a4l_lock_t mite_channel_lock; \
                                                                \
        int changain_state;                                     \
        unsigned int changain_spec;                             \
                                                                \
        unsigned int caldac_maxdata_list[MAX_N_CALDACS];        \
        unsigned short ao[MAX_N_AO_CHAN];                                       \
        unsigned short caldacs[MAX_N_CALDACS];                          \
                                                                \
        unsigned short ai_cmd2; \
                                                                \
        unsigned short ao_conf[MAX_N_AO_CHAN];                          \
        unsigned short ao_mode1;                                \
        unsigned short ao_mode2;                                \
        unsigned short ao_mode3;                                \
        unsigned short ao_cmd1;                                 \
        unsigned short ao_cmd2;                                 \
        unsigned short ao_cmd3;                                 \
        unsigned short ao_trigger_select;                       \
                                                                \
        struct ni_gpct_device *counter_dev;     \
        unsigned short an_trig_etc_reg;                         \
                                                                \
        unsigned ai_offset[512];                                \
                                                                \
        unsigned long serial_interval_ns;                       \
        unsigned char serial_hw_mode;                           \
        unsigned short clock_and_fout;                          \
        unsigned short clock_and_fout2;                         \
                                                                \
        unsigned short int_a_enable_reg;                        \
        unsigned short int_b_enable_reg;                        \
        unsigned short io_bidirection_pin_reg;                  \
        unsigned short rtsi_trig_direction_reg;                 \
        unsigned short rtsi_trig_a_output_reg; \
        unsigned short rtsi_trig_b_output_reg; \
        unsigned short pfi_output_select_reg[NUM_PFI_OUTPUT_SELECT_REGS]; \
        unsigned short ai_ao_select_reg; \
        unsigned short g0_g1_select_reg; \
        unsigned short cdio_dma_select_reg; \
        \
        unsigned clock_ns; \
        unsigned clock_source; \
        \
        unsigned short atrig_mode;                              \
        unsigned short atrig_high;                              \
        unsigned short atrig_low;                               \
        \
        unsigned short pwm_up_count;    \
        unsigned short pwm_down_count;  \
        \
        sampl_t ai_fifo_buffer[0x2000];                         \
        uint8_t eeprom_buffer[M_SERIES_EEPROM_SIZE]; \
        \
        struct mite_struct *mite; \
        struct mite_channel *ai_mite_chan; \
        struct mite_channel *ao_mite_chan;\
        struct mite_channel *cdo_mite_chan;\
        struct mite_dma_descriptor_ring *ai_mite_ring; \
        struct mite_dma_descriptor_ring *ao_mite_ring; \
        struct mite_dma_descriptor_ring *cdo_mite_ring; \
        struct mite_dma_descriptor_ring *gpct_mite_ring[NUM_GPCT]; \
        subd_8255_t subd_8255


typedef struct {
        ni_board *board_ptr;
        NI_PRIVATE_COMMON;
} ni_private;

#define devpriv ((ni_private *)dev->priv)
#define boardtype (*(ni_board *)devpriv->board_ptr)

/* How we access registers */

#define ni_writel(a,b)  (writel((a), devpriv->mite->daq_io_addr + (b)))
#define ni_readl(a)     (readl(devpriv->mite->daq_io_addr + (a)))
#define ni_writew(a,b)  (writew((a), devpriv->mite->daq_io_addr + (b)))
#define ni_readw(a)     (readw(devpriv->mite->daq_io_addr + (a)))
#define ni_writeb(a,b)  (writeb((a), devpriv->mite->daq_io_addr + (b)))
#define ni_readb(a)     (readb(devpriv->mite->daq_io_addr + (a)))

/* INSN_CONFIG_SET_CLOCK_SRC argument for NI cards */
#define NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC  0 /* 10 MHz */
#define NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC        1 /* 100 KHz */

#endif /* _ANALOGY_NI_STC_H */